Digital Engineer 3Vets2industry • Chandler, AZ, US
Digital Engineer 3
Vets2industry • Chandler, AZ, US
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job_description.job_card.job_descriptionFPGA design engineer with at least 5 years of VHDL design experience for use in aerospace avionics applications. Design and deliver production quality FPGA releases from initial proof of concept up to production. FPGAs and SoCs such as Microsemi (Polar Fire, Smart Fusion), Xilinx FPGAs and SoCs (MP SoC, RF SoC). Digital signal processing and fixed point math with knowledge of scaling / saturation in FPGAs. Model-based FPGA design porting C / C++ or MATLAB code to VHDL targeting FPGAs / SoCs. Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS). Translate system level requirements into FPGA requirements. Design and code in VHDL for reliability and maintainability. Design, analysis, simulation, test, and integration of digital electronic modules and / or CCAs for Launch Vehicle applications. Industry interfaces, such as Space Fiber, PCIe, Ethernet, I2C, SPI, and UART. Familiarity with designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage is a plus. On-site with hybrid possibility. This position is for our direct client, a large federal contractor. W2 Only, no 3rd party corp to corp engagement. All your information will be kept confidential according to EEO guidelines.
Digital Engineer 3
- Chandler, AZ, USA
- Contract
- Up to $75 an hour
Company Description
King Global Enterprise Solutions (KGES) is supporting USG1 (www.usg1.com), which provides top talent and technology solutions to government agencies. We aim to make a meaningful difference and add value to the mission. We look for candidates who want to make a difference to their team and its objectives. In return, we will support you and help you in your goals and career journey.
Job Description
USG1 is seeking multiple FPGA design engineers for our direct client, a large federal contractor.
Qualifications
Candidate does not need to have validation experience but should have some understanding of self-check VHDL test benches and digital signal processing using FPGAs.
Additional Information
J-18808-Ljbffr
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Digital Engineer • Chandler, AZ, US
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