Hardware Developer

IBM Corporation, Austin, Texas (Up to 20% telecommuting permitted) : Perform Microprocessor Chip Hardware Static Timing Analysis and is responsible for ensuring that the electrical timing characteristics of the physical implementation of a microprocessor chip design meet stringent performance and reliability requirements. Applying electrical engineering principles to analyze and validate the timing of digital circuits without requiring simulation vectors. Coordinate with cross-functional teams, including logic designers, physical designers, integrators, and architects, to achieve functional and test timing closure goals during floor planning, synthesis, and routing. Build and maintain timing environments compatible with Git, ensuring synchronization with the latest tools and updates. Conduct timing runs across different PVT (Process-Voltage-Temperature) corners to ensure robust chip operation after validating input timing rules. Analyze timing data to track timing takedown processes, leveraging reports from various tools and databases. Define timing constraints across all design sub-units and ensure proper data transfers between different clock and power domains; address and resolve clock and power domain crossing issues to ensure proper timing alignment.  Conduct Electromigration and IR Drop Analysis by evaluating how electrical current and voltage drops affect timing paths and long-term reliability. Allocate and manage timing budgets for critical paths and interfaces, while building schematic models. Optimize power consumption by reviewing and adjusting timing requirements and ensuring all units meet timing goals. Conduct noise analysis runs to detect failures and provide resolutions. Identify and mitigate risks during the ECO (Engineering Change Order) process that could impact the project timeline. Leverage EDA (Electronic Design Automation) tools such as Synopsys PrimeTime and Cadence Tempus to evaluate and suggest enhancements for electrical timing sign-off and static timing analysis with the EDA team. Lead timing-related discussions in design reviews to ensure timing closure is on track. Maintain documentation to timing closure strategies and constraints. Provide support for test floor simulations to help identify issues and understand root causes. Continuously improve timing closure methodologies and mentor junior engineers by providing guidance on best practices. Utilize : Circuit Design Flow, Static Timing Analyzer, Statistical Timing Analyzer, Spice circuit simulator, AFS, Git, Hierarchical design and timing methodology. Required : Bachelor’s degree or equivalent in Electrical Engineering, Engineering or related and five (5) years of experience as a Technical Leader or related. Five (5) years of experience must include utilizing Circuit Design Flow, Static Timing Analyzer, Statistical Timing Analyzer, Spice circuit simulator, AFS, Git, Hierarchical design and timing methodology. $225000 to $244697 per year.  Please send resumes to . Applicants must reference H247 in the subject line.

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