Job Title : Sr ASIC / FPGA VHDL Design Engineer Job Code : 24260 Job Location : Camden, NJ-relocation available for those that qulify Schedule : 9 / 80 Regular with every other Friday off Job Description : Reporting to the Manager, Engineering (ASIC / FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design team, responsible for the delivery of FPGAs for defense applications. S / he will architect, implement FPGA design, with hands on design / debug with primarily Ethernet, I2C, SPI, AXI protocols. We are a learning organization and have the capability to target all FPGA vendors and have ASIC front end capability, with mature design processes. This is a high impact role in the organization to ensure robust quality and delivery of communication products for National Security. Derive FPGA design specifications from system requirements
Develop detailed FPGA architecture for implementation
Implement design in RTL (VHDL) and perform module level simulations
Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA)
Perform RTL quality using : Support Board, FPGA bring up
Validate design through HW / SW integration test with test equipment
Support product collateral for NSA certification Qualifications : Bachelor of Science (BS) -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical / Electronics / Computer Engineering / Computer Science)
3-5+ years’ experience designing FPGA products with VHDL
Active DoD Security Clearance Preferred Additional Skills : Experience in C++ (OOP)
Experience with Xilinx SoC design with SDKs and PetaLinux OS
Hiring Communication • Camden, NJ, United States