ASIC Engineer, Emulation (Austin)

ASIC Engineer, Emulation

Engineers with experience in HW emulation and prototyping required to build ASIC / System on Chip (SoC) and IP for data center applications.

Responsibilities

Deliver high-quality emulation and prototyping models on industry-standard emulation and prototyping platforms.

Design, build, and execute comprehensive emulation test plans to ensure model accuracy and support pre-silicon validation efforts.

Lead the development and adoption of best-in-class emulation methodologies to accelerate hardware verification and software development.

Collaborate with Design, DV, validation, and software teams to develop tools, flows, and mechanisms that demonstrate key performance indicators such as functionality, performance, and power efficiency.

Enhance and mature standard interfaces including PCIe, DDRx, USB, and other interfaces on emulation components such as speed bridges, transactors, and virtual components.

Continuously improve the efficiency and effectiveness of emulation components and workflows for testing, debugging, analysis, and automation.

Partner with vendors to troubleshoot issues, deploy new emulation capabilities, and drive ongoing improvements.

Minimum Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

6+ years of experience with EDA tools and scripting languages used to build tools and flows for complex emulation environments.

Experience with current emulation technologies and methods, simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods.

Preferred Qualifications

Track record of successful ASIC / SoC where emulation is a critical workflow.

Experienced in compilation and build flows and creating build flows from scratch with necessary design modifications for emulation.

Experience in creating emulation systems for Multi-chip / SoC / IP designs and understanding of trade-offs between emulation resource consumptions, performance and ease of debug.

Experience managing multiple programs and enabling verification to achieve coverage closure and SW to achieve left shift of software development.

Experience with SystemVerilog and C++ to model RTL components and transactors.

Experience with post-silicon bring up, debug, and reproducing issues on emulators.

Experience with cadence (palladium / protium) and Synopsys (zebu) tools.

Experience with scripting languages such as Python, Perl and TCL.