Electronic Design Automation (EDA) Engineer

Job Title : Electronic Design Automation (EDA) Engineer Job Location : San Jose, CA 95113 Onsite Requirements : C++ EDA HDL Job Description : Design and develop of tools that help hardware designers and security architects identify security flaws in their architecture and hardware designs.

All potential candidates should read through the following details of this job with care before making an application.

Defining algorithms / heuristics for instrumenting and identifying hardware security issues in designs described in an HDL.

Efficiently implementing those solutions that are effective and performant on multi-billion gate designs in our Radix tool suite.

Working within and extending our existing Radix tool C++ infrastructure.

Qualifications and Skills : Bachelor's degree in Computer Science / Engineering (MS / PhD preferred) Expert level engineer with a minimum of 8 years working on a commercial EDA tool as a mainstream R&D developer of the core engine.

Solid understanding and experience with hardware description languages (Verilog, SystemVerilog, VHDL) and simulation semantics.

Expert programming and debug skills in modern C++.

Demonstrated deep knowledge in design and architecture of efficient, scalable software systems and data structures to support compilation of billion gate designs, including performance profiling and optimizing large code bases.

Expert proficiency in algorithms and data structures for digital logic.

Experience in multi-threading, multi-tasking and job distribution to support analysis and netlist transformations to minimize runtime and memory footprint.

Ability to operate in a small team and be an effective communicator.

Proficiency working in Linux.

This position can be based anywhere in the continental USA.

Preferred Qualifications : Relevant work experience is in the domains of Simulation, Synthesis or Formal Verification or similar products.

Python scripting for prototyping and test automation.

Understanding of SQL or other database formats for managing large datasets.

Understanding of RTL / gate-level simulation and debugging.

Experience in the implementation and verification of SoC designs.

A background in Computer Security or familiarity with Computer Security topics.

Role / Skills : EDA means Electronic Design Automation which is in places like Synopsys, Cadence, Siemens (formerly Mentor Graphics), Ansys (now acquired), etc.

Would consider someone with many years of hardware design with VHDL / SystemVerilog PLUS years of deep C++ experience in scalable software as a POTENTIAL substitute for the EDA experience.

Should have a strong C++ Coding Background (8-10 years+), can run a simulator, has worked with Verilog, and knows HDL thoroughly.

Can hit the ground running, jump in and learn the C++ code and add login into it.

This is NOT Embedded Software, FPGA Design, or ASIC Design.

• 3rd party and subcontract staffing agencies are not eligible for partnership on this position.

3rd party subcontractors need not apply.

This position requires candidates to be eligible to work in the United States, directly for an employer, without sponsorship now or anytime in the future.

This client is a US Federal Government contractor and is legally required to hire US Citizens.

US Citizens will only be considered for this role