Job Title : Sr. DSP R&D Engineer – C / C++, Wireline, Simulink, ASIC
Company : Motion Recruitment
Job Description : Our client is a global infrastructure technology leader with over 60 years of innovation in the semiconductor and manufacturing space for communications. They are urgently seeking a senior-level Digital Signal Processing (DSP) R&D Engineer to join their growing team.
Responsibilities include :
- Develop specifications, architecture, and micro-architecture of digital signal processing and communication algorithms
- Perform bit-exact MATLAB / Simulink and C / C++ system modeling and simulation
- Develop and execute system-level simulation suites for copper Ethernet PHY transceivers and verify with RTL simulations
- Define and document chip requirements, architecture, verification, and lab test plans
- Conduct lab testing and debugging of ASICs
- Create documentation, application notes, and provide customer support
Requirements :
Master's degree with 3+ years of related experience or PhD in Digital Signal ProcessingKnowledge of communication theory and digital signal processing algorithmsExperience with equalizers, timing recovery, echo cancellation, and gain control algorithmsProficiency in C / C++, MATLAB / SimulinkExperience designing communication systems for high-performance ASIC products is highly desirableHands-on lab skillsExcellent verbal and written communication skillsMust have experience with wireline algorithms and Ethernet 802.3 PHY transceiversThe Offer :
Salary : $140,000 - $180,000Full medical, dental, vision insurance401K planPTO and bonus potentialLocation : Irvine, CA
Job Date : Wed, 11 Jun 2025
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