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Sr. DSP R&D Engineer - C / C++, Wireline, Simulink, ASIC
Tech CraticIrvine, CA, USjob_description.job_card.variable_days_ago
serp_jobs.job_preview.job_type
- serp_jobs.job_card.full_time
job_description.job_card.job_descriptionMaster's degree with 3+ years of related experience or PhD in Digital Signal Processing Knowledge of communication theory and digital signal processing algorithms Experience with equalizers, timing recovery, echo cancellation, and gain control algorithms Proficiency in C / C++, MATLAB / Simulink Experience designing communication systems for high-performance ASIC products is highly desirable Hands-on lab skills Excellent verbal and written communication skills Must have experience with wireline algorithms and Ethernet 802.3 PHY transceivers Salary : $140,000 - $180,000 Full medical, dental, vision insurance 401K plan PTO and bonus potential
Job Title : Sr. DSP R&D Engineer – C / C++, Wireline, Simulink, ASIC
Company : Motion Recruitment
Job Description : Our client is a global infrastructure technology leader with over 60 years of innovation in the semiconductor and manufacturing space for communications. They are urgently seeking a senior-level Digital Signal Processing (DSP) R&D Engineer to join their growing team.
Responsibilities include :
- Develop specifications, architecture, and micro-architecture of digital signal processing and communication algorithms
- Perform bit-exact MATLAB / Simulink and C / C++ system modeling and simulation
- Develop and execute system-level simulation suites for copper Ethernet PHY transceivers and verify with RTL simulations
- Define and document chip requirements, architecture, verification, and lab test plans
- Conduct lab testing and debugging of ASICs
- Create documentation, application notes, and provide customer support
Requirements :
The Offer :
Location : Irvine, CA
Job Date : Wed, 11 Jun 2025
Apply for this job now!
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Dsp • Irvine, CA, US