As a Senior Design Verification Engineer, you will play a key role in verifying our innovative RF sensing and communications SoCs based on the Edge Processing Unit (EPU).
You will own end-to-end verification at the unit, integration, and SoC levels, collaborating closely with RTL engineers and the DV team to ensure robust, high-quality designs delivered on time.
Responsibilities :
Develop verification plans, test strategies, and coverage metrics for RISC-V processor-based designs, including custom RVV and extensions.
Architect and implement reusable testbenches for unit, integration, and SoC-level verification using SystemVerilog Testbench (SVTB) and UVM methodologies.
Build constrained-random verification environments with functional coverage, execute native RISC-V assembly and C code tests.
Develop and verify assertions; perform formal verification to validate design against specifications.
Ensure functional and code coverage closure, debug RTL and testbench issues, and optimize verification efficiency through testbench reuse.
Work closely with RTL, DV, and DFT teams, participate in design and verification reviews, and contribute in an agile development environment.
Qualifications :
Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field.
At least 5 years of experience in processor design verification, preferably RISC-V.
Experience with complex processor architectures, vector extensions, and custom instructions.
Verification of high-bandwidth, low-power signal processing or AI designs is a plus.
Expertise in SystemVerilog Testbench (SVTB) and UVM.
Strong knowledge of constra ined-random verification with functional coverage.
Hands-on experience in formal verification and assertion development.
Native processor code verification using RISC-V assembly and C.
Proficiency with simulators and debuggers such as VCS, ModelSim, or QuestaSim.
Familiarity with Python, Perl, or Shell scripting for automation.
Excellent problem-solving, debugging, communication, and teamwork abilities, proactive and self-motivated in a fast-paced startup environment.
Design Verification Engineer • Irvine, CA, United States