Lattice is hiring : Design Eng 2 in New York

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast-paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills We are looking for a passionate digital design engineer to build a High Speed Serial Protocol Hard-IP portfolio for Lattice FPGA. The individual should have the ability to work closely with Principal Engineers or Architects to translate specifications into RTL design for optimal performance, low power consumption, and efficient logic utilization.

Accountabilities / Exposure :

Own unit-level design and IP integration.

Conduct design quality checks using industry-standard EDA tools and methodologies.

Define design timing constraints and achieve timing convergence.

Plan open-box testing, write assertion checks, and debug.

Perform code coverage analysis and ensure closure.

Support silicon power-on and post-silicon validation.

Develop new design methodologies.

Automate design flows through scripting for daily tasks.

Prepare design documentation, including micro-architecture and implementation details.

Qualifications :

Good understanding of ASIC / FPGA IP or SoC development cycles.

Knowledge of High-Speed Serial Protocols such as Ethernet, PCIe, MIPI, or Universal Transceivers.

Proficiency in RTL design using Verilog or SystemVerilog and design constraints.

Experience with design quality check methodologies like Lint, CDC, RDC, Fishtail, or UPF flows.

Advanced skills in logic simulation using EDA tools such as Cadence Xcelium, Synopsys VCS, or Siemens Questa.

Experience collaborating with Design Verification teams on test planning, assertions, functional and code coverage, and debugging.

Familiarity with Physical Design processes like Synthesis, LEC, or Timing Closure.

Programming skills in Perl, Shell Scripting, TCL, Java, Python, or C / C++, and familiarity with Linux OS.

Experience in technical writing, including micro-architecture documentation, publications, or patents.

Self-motivated with strong communication skills, promoting innovation and teamwork.

Experience with silicon power-on or hardware validation is a plus.

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