Memory Sub-System Validation Engineer- HBM / DDR for GPU / CPU

Overview

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

The Role

The Datacenter Graphics and Accelerated Computing Validation Team is looking for a dynamic and energetic person to join our growing post-silicon validation team. The High-Bandwidth Memory (HBM) sub-system is a niche technology, that delivers industry leading Datacenter solutions for Machine Learning (ML), and High-Performance Computing (HPC). Memory Validation engineer is responsible to drive and deliver pre- and post-silicon validation and characterization of on-die HBM or off-die DDR Memory on AMD\'s Datacenter GPU (Machine Instinct product). In this wide-ranging role, validation engineer is the critical interface between various teams; DRAM architecture & product engineering, Memory Controller Design and Software, DDR PHY, to ensure that advanced memory technologies are delivered from architecture to mass production to AMD\'s quality and industry standards. The validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

The Person

An experienced self-starter with the ability to execute complex test plans independently and collaborate with cross-function teams to debug and resolve issues. As a valued team member, you are expected to lead by example, and mentor junior engineers. You should be hands-on with lab tools and comfortable working in a lab environment.

Key Responsibilities

Memory Sub-system Validation Engineer\'s responsibility includes all aspects of pre- and post-silicon validation from planning, execution and debug. Develop and execute test plans for HBM Functional and Electrical Validation (PVT Shmoo Characterization). The sought-after candidate possesses extensive knowledge of high bandwidth memory subsystem, including SoC memory architecture, Unified Memory controller, PHY design and high speed IO interface, DRAM device, and associated calibration / training mechanisms.

Key Qualifications

• Ability to apply knowledge of other high-speed, high-performance memory technologies
• Experience working with major DRAM memory vendors and validation of DRAM device is a plus.
• Debug skills to root cause post-production issues, customer returns
• Proven ability to drive resolution of critical problems, able to comfortable working in lab environment

Preferred Experience

Academic Credentials

Bachelors or Masters in Electrical or Computer Engineering + minimum 5-7 years experience

Location

Austin, Texas

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Benefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants\' needs under the respective laws throughout all stages of the recruitment and selection process.

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