SystemVerilog / UVM Design Verification Test Engineer

Duration : 5 / 6 Months Hybrid Job Description : We are seeking a highly skilled and meticulous SystemVerilog / UVM Design Verification Test Engineer to play a crucial role in validating our complex System-on-Chip (SOC) and Integrated Circuit (IC) designs. This role requires expert-level proficiency in SystemVerilog and UVM, a strong understanding of processor architectures, and high-speed protocols. Responsibilities : Architect, develop, and maintain advanced verification environments (Testbenches) using UVM and SystemVerilog to ensure functional correctness and achieve aggressive coverage goals for complex SOC features. Develop and execute comprehensive verification test plans for key SOC blocks, with a focus on ARM processor subsystems and high-speed interfaces. Implement test cases and scenarios to rigorously verify the functionality and compliance of PCI Express (PCIe) and high-speed Ethernet controllers, leveraging UVM sequences, scoreboards, and monitors. Develop, maintain, and optimize Python scripts to automate verification flows, process simulation results, drive coverage closure, and manage large-scale regression suites. Analyze simulation results, track coverage metrics, and debug failures down to the register-transfer level (RTL) using waveform viewers and logic analyzers. Collaborate closely with Design, Firmware, and Hardware teams to define interfaces, triage reported bugs, and contribute to post-silicon validation strategy. Experience (Required) : 3+ years of professional experience specifically in IC / SOC Design Verification (DV). Mandatory expert-level proficiency in SystemVerilog and UVM (Universal Verification Methodology). Demonstrated ability to build UVM testbenches from scratch and contribute significantly to UVM environment architecture. Demonstrated experience verifying processor subsystems (e.g., CPU clusters, interconnects) based on ARM architecture (or equivalent). Strong expertise in verifying high-speed communication controllers, specifically PCI Express (PCIe) and / or high-speed Ethernet, within a UVM framework. Proficiency in Python scripting for verification automation, data analysis, and regression management. Deep knowledge of coverage-driven verification (CDV) techniques and methodologies for achieving functional and code coverage closure. Experience (Desired) : Experience with OVM and transition / migration to UVM. Familiarity with Post-silicon validation methodologies and lab debug. Knowledge of embedded firmware or driver development (C / C++) to aid in co-simulation or system-level testing. Experience in applying advanced verification techniques like formal verification or emulation. Familiarity with TCL / Perl for utility scripting alongside Python. Education : Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. About US Tech Solutions : US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.