Talent.com
Senior ASIC Design Engineer – Clocks IP

Senior ASIC Design Engineer – Clocks IP

NVIDIA CorporationSanta Clara, CA, United States
job_description.job_card.variable_days_ago
serp_jobs.job_preview.job_type
  • serp_jobs.job_card.full_time
job_description.job_card.job_description

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today.The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab.

  • What you'll be doing :
  • As a Clocks team member, you will be architecting the clock domain to satisfy functional, physical and testing design requirements.
  • Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural / design / physical constraints.
  • Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
  • Collaborate with Physical design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking.
  • Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams.
  • Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
  • What we need to see :
  • BS in Electrical Engineering or equivalent experience (MS preferred)
  • 3+ years of relevant work experience.
  • Deep understanding of logic optimization techniques and PPA trade-offs.
  • Excellent interpersonal skills and ability to collaborate with multiple teams.
  • Experience in RTL design (Verilog), verification and logic synthesis.
  • Strong coding skills in python or other industry-standard scripting languages.
  • Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.
  • Implementing on-chip clocking networks is a bonus
  • Ways to stand out from the crowd :
  • Experience with clocks controller, clocks logic design
  • Understanding of system level artifacts like power, noise, etc
  • Experience with scalable designs and architecture.
  • Hands- on silicon debug is a plus.#LI-HybridYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and .Applications for this job will be accepted at least until October 3, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

#J-18808-Ljbffr

serp_jobs.job_alerts.create_a_job

Asic Design Engineer • Santa Clara, CA, United States

Job_description.internal_linking.related_jobs
  • serp_jobs.job_card.promoted
ASIC Design Engineer Staff

ASIC Design Engineer Staff

Hewlett Packard Enterprise Development LPSan Jose, CA, United States
serp_jobs.job_card.full_time
Responsibilities : • • - Work with Physical design team for optimal floorplan and timing closure.Identify and fix timing in RTL to meet the frequency target. Work with the Verification team to make sur...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_1_day
  • serp_jobs.job_card.promoted
Senior Design Engineer – Coherent Interconnect

Senior Design Engineer – Coherent Interconnect

Tachyum Inc.Santa Clara, CA, United States
serp_jobs.job_card.full_time
Working with a small team to implement, debug, and verify a high-performance coherence management system.Build the infrastructure to support integrity testing and debug on emulation system.Requires...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_variable_days
  • serp_jobs.job_card.promoted
High Speed Analog / Mixed-Signal IC Design Engineer

High Speed Analog / Mixed-Signal IC Design Engineer

Apple Inc.Cupertino, CA, United States
serp_jobs.job_card.full_time
High Speed Analog / Mixed-Signal IC Design Engineer.Cupertino, California, United States Hardware.In this role, you will leverage your expertise to develop cutting-edge circuits and architectures for...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_30
  • serp_jobs.job_card.promoted
Senior Mixed Signal Design Engineer

Senior Mixed Signal Design Engineer

NVIDIA CorporationSanta Clara, CA, United States
serp_jobs.job_card.full_time
Senior Mixed Signal Design Engineer (Finance).NVIDIA has continuously reinvented itself over two decades.Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined moder...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_30
  • serp_jobs.job_card.promoted
Manager, ASIC Design

Manager, ASIC Design

Meta PlatformsSunnyvale, CA, US
serp_jobs.job_card.full_time
Meta is hiring an Asic Design Manager within our Infrastructure organization to support the Front-End Design function.We are seeking a technical manager who is a consensus-driven leader, with demon...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_variable_days
  • serp_jobs.job_card.promoted
Analog / Mixed-Signal IC Design Engineer

Analog / Mixed-Signal IC Design Engineer

Ipro Networks Pte. Ltd.Santa Clara, CA, United States
serp_jobs.job_card.full_time
Analog / Mixed-Signal IC Design Engineer.Santa Clara, CA | RTO 5 Days Required.serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_variable_days
  • serp_jobs.job_card.promoted
Sr. ASIC Engineer III, Annapurna Labs

Sr. ASIC Engineer III, Annapurna Labs

AmazonCupertino, CA, United States
serp_jobs.job_card.full_time
AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released ne...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_30
  • serp_jobs.job_card.promoted
Ethernet ASIC Design Engineer

Ethernet ASIC Design Engineer

Cornelis Networks, Inc.San Jose, CA, United States
serp_jobs.job_card.full_time
Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters.Our differentiated architecture seamlessly integrates hardware, software and sys...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_variable_days
  • serp_jobs.job_card.promoted
Manager, ASIC Design Sunnyvale, CA +1 locations • Infrastructure • Engineering +2 more Infrastr[...]

Manager, ASIC Design Sunnyvale, CA +1 locations • Infrastructure • Engineering +2 more Infrastr[...]

MetaSunnyvale, CA, United States
serp_jobs.job_card.full_time
Manager, ASIC DesignMeta is hiring an ASIC Design Manager within our Infrastructure organization to support the Front-End Design function. We are seeking a technical manager who is a consensus-drive...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_variable_days
  • serp_jobs.job_card.promoted
Senior RTL Design Engineer

Senior RTL Design Engineer

IC ResourcesSan Francisco, CA, United States
serp_jobs.job_card.full_time
This role will deliver the bandwidth, latency, and power profile needed for large-scale compute.Architect and implement memory controllers for HBM2E / 3, LPDDR5 / 6, and DDR5.Deliver RTL from spec to t...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_variable_days
  • serp_jobs.job_card.promoted
Senior RTL Design Engineer

Senior RTL Design Engineer

Advanced Micro Devices, Inc.San Jose, CA, United States
serp_jobs.job_card.full_time
WHAT YOU DO AT AMD CHANGES EVERYTHING.We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that ...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_variable_days
  • serp_jobs.job_card.promoted
ASIC Engineer, Design Sunnyvale, CA +1 locations • Infrastructure • Design +2 more Infrastructu[...]

ASIC Engineer, Design Sunnyvale, CA +1 locations • Infrastructure • Design +2 more Infrastructu[...]

MetaSunnyvale, CA, United States
serp_jobs.job_card.full_time
Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, network acceleration and video transcoding.We are looking...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_30
  • serp_jobs.job_card.promoted
Senior ASIC Design Engineer

Senior ASIC Design Engineer

Cornelis Networks, Inc.San Jose, CA, United States
serp_jobs.job_card.full_time
Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters.Our differentiated architecture seamlessly integrates hardware, software and sys...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_variable_days
  • serp_jobs.job_card.promoted
ASIC Engineer, Design Sunnyvale, CA +1 locations • Data Center +3 more • Engineering +2 more Da[...]

ASIC Engineer, Design Sunnyvale, CA +1 locations • Data Center +3 more • Engineering +2 more Da[...]

MetaSunnyvale, CA, United States
serp_jobs.job_card.full_time
ASIC Engineer, DesignASIC Engineer, Design Responsibilities • Architecture exploration • Micro-architecture development • Soft and hard IP identification, selection and integration.Collaboration with ...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_variable_days
  • serp_jobs.job_card.promoted
Senior Digital Design Engineer

Senior Digital Design Engineer

TPI Global SolutionsSan Francisco, CA, United States
serp_jobs.job_card.full_time
Direct message the job poster from TPI Global Solutions.Talent Acquisition Professional, Hiring Candidates for Semiconductor & Automotive Domain (DV, PD, RTL, ASIC, FPGA, PCB,Layout,Storage,Firmwar...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_variable_days
  • serp_jobs.job_card.promoted
Senior ASIC Design Engineer (eInfochips Inc)

Senior ASIC Design Engineer (eInfochips Inc)

Arrow Electronics Australia Pty LtdSan Jose, CA, United States
serp_jobs.job_card.full_time
Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and cont...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_variable_days
  • serp_jobs.job_card.promoted
ASIC Design Engineer

ASIC Design Engineer

Apple Inc.Santa Clara, CA, United States
serp_jobs.job_card.full_time
Santa Clara, California, United States Hardware.The ideal candidate will have experience in ASIC design with : - Architecture research and / or development of memory or highly interconnected system arc...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_30
  • serp_jobs.job_card.promoted
Senior ASIC Physical Design Engineer, Netlisting

Senior ASIC Physical Design Engineer, Netlisting

NVIDIA CorporationSanta Clara, CA, United States
serp_jobs.job_card.full_time
NVIDIA has continuously reinvented itself over two decades.Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parall...serp_jobs.internal_linking.show_moreserp_jobs.last_updated.last_updated_variable_days