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DSP System Architect

DSP System Architect

Credo Semiconductor, Inc.San Jose, CA, United States
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DSP System Architect

We are seeking a DSP System Architect to optimize digital signal processing (DSP) architectures for high-speed SerDes (Serializer / Deserializer) transceivers. This role defines system-level architecture, algorithms, and performance needs. The architect will work closely with cross-functional teams to debug, analyze data and bring SerDes solutions to market.

Responsibilities

  • Collaborate with analog, digital, and mixed-signal design teams to implement DSP solutions.
  • Collaborate with application and firmware teams to participate in silicon bring-up and debugging by analyzing data and providing guidance on test plans for lab characterization and verification.
  • Assist customers on system-level performance and algorithmic issues.
  • Define and design DSP architectures for high-speed SerDes and optical transceivers.
  • Develop and maintain end-to-end system models using tools like MATLAB, Simulink, C, and / or Python.
  • Design and simulate DSP algorithms for signal processing in high-speed links, including equalization, timing recovery, and error correction (FEC).
  • Perform research and development activities to advance DSP for SerDes and optical channels.
  • Develop and perform behavioral modeling of mixed-signal circuit designs for transceivers.

Qualifications

  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
  • 0-7+ years of experience in DSP system architecture and algorithm development for high-speed SerDes or communication systems.
  • Understanding of digital communication and signal processing theory, including :
  • Channel equalization techniques (e.g., FFE, DFE)
  • Timing recovery and CDR (Clock and Data Recovery) architectures
  • Detection and estimation theory
  • Adaptive algorithms and system identification
  • Proficiency in communication system modeling using tools like MATLAB, Simulink, C, and / or Python.
  • Experience with high-speed serial data protocols (e.g., NRZ, PAM4) and relevant industry standards.
  • Familiarity with mixed-signal circuit design concepts and their impact on DSP performance.
  • Experience in guiding and testing the transfer of algorithms from high-level models to RTL implementation.
  • Communication, problem-solving, and collaboration skills.
  • Preferred Skills

  • Experience with advanced modulation formats (e.g., PAM4).
  • Experience with ADC-based wireline transceivers and / or coherent DSP architectures.
  • Familiarity with FEC (Forward Error Correction) techniques, such as RS or LDPC codes.
  • Familiarity with lab equipment for testing high-speed serial links (e.g., oscilloscopes, spectrum analyzers).
  • Experience with machine learning concepts and their application in DSP.
  • Knowledge of analog mixed-signal circuit design concepts.
  • Experience in firmware or embedded software development.
  • #J-18808-Ljbffr

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