FPGA / ASIC Design Engineer (Active / Current Secret Security Clearance)

FPGA / ASIC Design Engineer position in Reston, VA.

US Citizenship is required for this position

Active / Current Secret Security Clearance IS REQUIRED to apply for this position

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Shift 8 : 00 AM start time with every other Friday off (9 / 80 work schedule)

Work will be onsite

Job Description :

Reporting to the Manager, Engineering (ASIC / FPGA), the Design Engineer will be part of the key ASIC / FPGA design team, responsible for the delivery of FPGA / ASICs for high-speed crypto applications.

S / he will architect, implement high speed crypto architectures, on ASICs / Xilinx Zynq / MPSOC class FPGAs, with hands on design / debug with Ethernet, TCP / IP protocols.

L3Harris has state-of-the-art EDA flows / methodologies including Synopsys DC / Primetime / Synplify, Xilinx / Intel / Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS).

This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.

Skills / Experience :

Bachelor's Degree in Electrical Engineering or equivalent degree , and minimum 4 years of prior relevant experience (or Master's Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications / networking ASIC / FPGA products.

Possess an active SECRET Clearance

Experience mapping algorithms and standards (Ethernet, TCP / IP, AXI) to hardware and architecture / system design tradeoffs.

Proficient in VHDL design process and FPGA flow

Knowledge of Ethernet, TCP / IP protocols

Strong logic / board debug, and analytical skills.

Excellent written, verbal, and presentation skills.

A PLUS for prior experience with :

High Level Synthesis (HLS) with Vivado,

Embedded SW C++ (OOP) and System Verilog Assertions (SVA)

Knowledge of high-speed protocols (PCIe, TCP / IP, Ethernet)

VHDL Experience is required for all candidates to be considered.

1. Looking for mid-senior level folks

2. Proficient in VHDL >

5 yrs, Xilinx FPGA design EDA- Vivado

3. Must have done hands on multiple complex designs arch / design / verification / Synthesis / STA

4. Big Plus

a. Working with Ethernet protocol (not just instantiating the IP) Is a big plus.

b. Mentor EDA CDC / Lint / AC / RDC

Required Skills :

Derive engineering specifications from system requirements and develop detailed architecture

Execute design (RTL AND / OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)

Generate test plans

Perform module level verification, synthesis / STA, Lab debug, SW driven validation on Linux based SOC evaluation boards

Silicon / FPGA bring up, characterization and production ramp / support / collateral

Desired Skills : (Not Required)

Prior experience in Aerospace / Defense

Experience in C++ (OOP)

Experience in Xilinx MPSOC design with writing / debugging with SDKs, BSPs on bare metal / PetaLinux OS.

Experience with High level synthesis (Xilinx Vivado HLS, AND / OR Mentor Calypto).

Experience with Universal Verification Mythology (UVM)

Experience with project leadership and EVM

Degree Requirements :

Bachelor's Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Master's Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications / networking ASIC / FPGA products.

Pre-Screen Questions

Must haves for all candidates :

4-6 years of minimum experience VHDL experience

Extensive FPGA design going through design and verification process

Ethernet framing and protocol experience in FPGA

Active Secret Clerance

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