1 day ago Be among the first 25 applicants
Get AI-powered advice on this job and more exclusive features.
Online Advertisements
Senior Staff Design Verification Engineer (Ref # : 00066580) (Arteris, Inc. dba Arteris IP; Austin TX) : Advanced UVM based test bench development and debugging. Defining, documenting, developing, and executing RTL verification test and coverage at system level. Performance verification and power-aware verification. Triaging Regressions, Debugging RTL designs in Verilog and System Verilog. Help improve and refine verification process, methodology, and metrics. UVM expertise on complex SoC projects from test bench development to verification closure. Provide technical guidance to Junior engineers and contractors in the development
Online Advertisements
Senior Staff Design Verification Engineer (Ref # : 00066580) (Arteris, Inc. dba Arteris IP; Austin TX) : Advanced UVM based test bench development and debugging. Defining, documenting, developing, and executing RTL verification test and coverage at system level. Performance verification and power-aware verification. Triaging Regressions, Debugging RTL designs in Verilog and System Verilog. Help improve and refine verification process, methodology, and metrics. UVM expertise on complex SoC projects from test bench development to verification closure. Provide technical guidance to Junior engineers and contractors in the development
process of testbench. Organize progress meetings with Junior engineers and contractions in the development process. Review testbench code and able to identify holes and improvements. Responsible for sub-system level verification tasks which are higher level than block level. Communicate and co-ordinate development tasks with peer teams like Software and Application Engineering teams. Partial remote work permitted with direct reporting to 9601 Amberglen Blvd. Suite 117 Austin, TX 78729.
Salary : $165,000 - $210,000 per year
Apply online at www.arteris.com / careers / open-positions / ?p=apply Must include Ref # : 00066580.
Seniority level
Seniority level
Mid-Senior level
Employment type
Employment type
Full-time
Job function
Job function
Engineering and Information Technology
Industries
Semiconductor Manufacturing
Referrals increase your chances of interviewing at Arteris by 2x
Sign in to set job alerts for "Senior Design Verification Engineer" roles.
Austin, TX $130,355.00-$221,603.00 4 days ago
Senior ASIC Front End Infrastructure Engineer
Austin, TX $184,000.00-$356,500.00 1 week ago
Austin, TX $143,300.00-$247,600.00 3 days ago
Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team
Austin, TX $150,000.00-$260,000.00 3 days ago
Austin, TX $150,000.00-$250,000.00 3 weeks ago
Austin, TX $119,800.00-$258,000.00 2 weeks ago
Sr Design Verification Engineer-Verilog / VLSI
Austin, TX $175,000.00-$200,000.00 2 weeks ago
Senior Design Verification Engineer – High-Performance DSPs
Austin, TX $114,000.00-$166,000.00 2 weeks ago
Austin, TX $156,000.00-$229,000.00 1 week ago
Austin, TX $114,000.00-$166,000.00 1 week ago
Austin, TX $136,000.00-$264,500.00 6 days ago
Austin, TX $142,000.00-$203,000.00 2 weeks ago
Austin, TX $170,000.00-$200,000.00 20 hours ago
Sr. Physical Design Verification Engineer, Annapurna Labs
Austin, TX $143,300.00-$247,600.00 2 days ago
Austin, TX $173,000.00-$249,000.00 2 weeks ago
Austin, TX $104,000.00-$212,200.00 1 week ago
Senior ASIC Physical Design and Timing Engineer
Austin, TX $136,000.00-$264,500.00 1 week ago
Austin, TX $129,800.00-$212,800.00 1 week ago
Austin, TX $129,800.00-$212,800.00 2 days ago
We're unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
J-18808-Ljbffr
Design Verification Engineer • Austin, TX, US