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Physical Design Engineer II (Silicon Engineering)
Physical Design Engineer II (Silicon Engineering)SPACE EXPLORATION TECHNOLOGIES CORP • Bastrop, TX, US
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Physical Design Engineer II (Silicon Engineering)

Physical Design Engineer II (Silicon Engineering)

SPACE EXPLORATION TECHNOLOGIES CORP • Bastrop, TX, US
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Overview

Physical Design Engineer (Silicon Engineering) based in Bastrop, TX. SpaceX is developing Starlink and cutting-edge ASICs for space and ground infrastructures worldwide.

We are seeking a motivated, proactive, and intellectually curious engineer to work with cross-disciplinary teams on next-generation ASICs. Your work will help deliver solutions that expand the performance and capabilities of the Starlink network.

Responsibilities

  • Perform partition synthesis and physical implementation steps (e.g., synthesis, floorplanning, power / ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks).
  • Develop / improve physical design methodologies and automation scripts for various implementation steps.
  • Collaborate with the ASIC design team to drive architectural feasibility studies, develop timing / power / area targets, and explore RTL / design tradeoffs.
  • Resolve design / timing / congestion and flow issues, identify potential solutions and drive execution.
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop.

Basic Qualifications

  • Bachelor's degree in electrical engineering, computer engineering or computer science.
  • 3+ years of professional experience working on RTL2GDSII physical design and / or physical design flow development.
  • Preferred Skills and Experience

  • Experience with industry-standard EDA tools, including understanding of their capabilities and underlying algorithms.
  • Knowledge of deep sub-micron FinFET and CMOS solid-state physics.
  • Understanding of CMOS digital design principles, standard cells and libraries.
  • Understanding of CMOS power dissipation in deep submicron processes (leakage / dynamic).
  • Familiarity with CMOS analog circuit and physical design.
  • Basic knowledge of DFT / Scan / MBIST / LBIST and their impact on physical design flows.
  • Self-driven, proactive, with a can-do attitude; able to learn and work in a dynamic group environment.
  • Additional Requirements

  • Must be willing to work extended hours and weekends as needed.
  • To conform to U.S. Government export regulations (ITAR), applicant must be a U.S. citizen or national, a U.S. lawful permanent resident, a Refugee, or an Asylee, or be eligible to obtain required authorizations from the U.S. Department of State.
  • SpaceX is an Equal Opportunity Employer. Employment is governed on the basis of merit, competence and qualifications and will not be influenced by race, color, religion, gender, national origin / ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, or any other legally protected status. Applicants requiring reasonable accommodation can contact EEOCompliance@spacex.com.

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