Staff Machine Learning ASIC Design Verification Engineer

Overview

QUALCOMM is the world's leading developer of next-generation wireless and multimedia technology.

We are searching for an ASIC design verification engineer interested in developing world-class solutions for the next generation of AI / ML HW IP.

Required Skills / Experience

• Strong analytical and debugging skills
• Good working experience with C / C++
• Strong knowledge of Object Oriented Programming (OOP) concepts
• Hardware verification languages (HVL) : SystemVerilog testbench (UVM), and / or SystemC
• Hardware description languages (HDL) : Verilog and SystemVerilog
• Knowledgeable in one or more of the following disciplines is preferred : Display (Pixel processing / composition / compression, MIPI DSI, DisplayPort, HDMI etc.), Bus / interconnect (AHB, AXI)
• Strong knowledge of digital circuits and event-driven simulators
• Knowledgeable with Perl, Python, TCL, tcsh, and GNU Make
• Strong communication skills (written and verbal) to convey complex information to peers.
• Detailed oriented and be able to plan and prioritize tasks effectively.

Preferred Qualifications

Clock domain crossing and reset architecture

Simulation and code coverage tools (VCS, Verdi, Modeltech / Questa, or Xcelium)

Minimum Qualifications

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