Senior DFx / RTL Engineer

Please note this posting is to advertise potential job opportunities. This exact role may not be open today, but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.

The application window is expected to close on 9 / 15 / 2025

This is an onsite role and will require working out of the Milpitas / San Jose office

Meet the Team :

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Your Impact :

You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.

Key Responsibilities :

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Work closely with the design / design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Minimum Qualifications :

Preferred Qualification :

Why Cisco?

#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we're "old" (36 years strong) and only about hardware, but we're also a software company. And a security company.

We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can't put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it).

Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart.

Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don't care. Tattoos? Show off your ink. Like polka dots? That's cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!