Job Title : Technologist, 3D Semiconductor Integration and Advanced Packaging EngineerJob Code : 16213Job Location : Palm Bay, FLJob Schedule : 9 / 80 (Every other Friday off!)Relocation : Relocation assistance is available to qualified applicants Job Description : Responsible for architecting 3D semiconductor packaging solutions and heterogeneous integration processes.
Work across the industry to identify partners, tools, and technologies to develop advanced packaging solutions for 3D-ICs, 2.
5D, chiplets, silicon interposers, and other applications utilizing high density interconnect such as wafer-to-wafer and die-to-wafer stacking.
This key role will provide technical insight for our existing technologies and develop new technologies to capture and lead new programs with our military, government, and commercial customers.
Come join out great team! Essential Functions : Technical team leadership focused on developing 3D heterogeneous packaging solutions such as fine pitch electrical interconnects, die-to-wafer, and wafer-to-wafer stacking.
Lead trades to evaluate technology integration strategies, process and metrology tools, and IP technology transfers.Lead intra and inter technology transfer for advanced packaging including process documentation (i.
e. PDKs, tool lists, process or record, etc.) process engineering (i.e. transfer tutorials, training, engineering support, reliability, etc.
and process calibration (test chip design, calibration wafers, etc.)Represent the organization as the prime technical contact on contracts and projects.
Interacts with senior external personnel on significant technical matters often requiring coordination between organizations.
Develop collaborative relationships with Engineering Managers and Program Leadership to support business demands including bid and proposal.
Domestic and International Travel Required up to 25% of timeQualifications : Bachelor’s Degree and a minimum of 9 years of prior relevant experience or Graduate Degree and a minimum of 7 years of prior related experience.
In lieu of a degree, minimum of 13 years of prior related experience.Ability to obtain a US government Top Secret SCI Security Clearance Experience in advanced semiconductor packaging technology development from R&D to Development and into ProductionExperience in BEOL (Back End of Line) processes including ASML i-line photolithography, microbumping, TSV plating, CMP, etc.
Preferred Additional Skills : Experience with IP licensing and technoloy transfer
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