Prodapt is looking for a Senior Physical Design Engineer who has extensive experience in the RTL2GDSII flows for complex SoCs using the latest Synopsys / Cadence tools and nodes such as 5 / 3nm.
1+ year Contract
Location : Austin, TX
Responsibilities :
- Review block-level / top-level clock specifications for completeness and feasibility
- Handle all the Physical design tasks (Floorplanning, Placement, Clocktree synthesis, Routing and Timing closure)
- Perform sign-off tasks
Experience :
- 7+ years of relevant physical design experience
- Experience in running physical-aware logic synthesis
- Experience with synthesis, Place & Route, STA, LEC, floorplanning, power estimation / planning, CTS, physical verification (DRC / LVS), cross-talk, EM / IR.
- Experience in Block-level and Full-chip floor-planning, power grid planning
- Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
- Experience with Python, TCL, Perl Programming
Education : Bachelors Degree
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