Senior Engineering Manager R&D - CPU and Server Platform HW Accelerators
CAROUSEL PARAGRAPH
- Palo Alto, California
- Product Dev Management
- R2200782
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Come join the CPU & Server Platform team responsible for HW and Platform enablement for ESXi operating system and core virtualization infrastructure at VMware.
In this role you will be leading the Hardware Accelerators team creating next generation HW accelerators that significantly influence Data center virtualization.
You would join a cross-discipline team of highly capable and motivated engineers, designers, and validators. You will have the opportunity to transform your ideas into World-changing technologies & Products for Datacenter growth.
Work with Research Groups, Platform Engineering teams at all layers of Hardware & Software - from FPGA to Firmware to OS (ESXi) to Hypervisors.
You will have the opportunity to influence external FPGA, Silicon & platform vendors and VMW partners.
- Manage the CPU and Server Platform HW accelerators team.
- Responsible for Macro & Micro architecture of the overall FPGA chip and the design, verification, debug of individual IP blocks
- Development and refinement of RTL design to target power, performance, and timing goals
- Own Micro-architecture development and specification from high-level arch exploration, through micro architectural research towards a detailed specification
- Provide support to HW validation to run simulations, work with S / W and other team members to predict and validate performance results
- Work with multi-functional engineering teams to implement physical design and delivery
- Lead collaborative technical discussions to drive resolution on issues with internal teams and external HW partners
- Develop knowledge of system architecture, technical debug & validation strategy
- Be able to work in a high demand, fast paced environment with lots of real-time problem solving and critical thinking
Skills & Experience Needed
- MS or PhD in Electrical, Electronics or Computer Engineering or equivalent
- Minimum of 5+ years managing FPGA / ASIC hardware design teams.
- 10+ years of experience in in ASIC & FPGA design & debug
- Knowledgeable of server system design and Architecture
- Knowledge of logic design principles along with timing and power implications
- Experience logic designer in Verilog or VHDL and familiar with ASIC or FPGA EDA tools
- Knowledgeable in programming / scripting (C / C++, Perl, Python etc.)
- Understanding of CPU and microcontroller designs, verification & debug
- Familiar with cache coherency protocol, and their implementation, verification, and debug.
- Familiar with SOC, inra- and inter-chip interconnect systems
- Baseline knowledge current standards interfaces, PCIe, DRAM, Networking, CXL etc.
- Must have good understanding and knowledge of high-speed board design and layout
- A great team player with good attitude, aptitude with can do drive
- Excellent oral, written communication and people, stakeholder management skills.
- Experience in full lifecycle from design to shipping of enterprise grade HW products
This job may require the candidate to comply with travel restrictions and / or work from a facility that requires full vaccination prior to entry.
Further, depending on various factors, including legal challenges to the Executive Order on Ensuring Adequate COVID Safety Protocols for Federal Contractors, VMware may require employees to be fully vaccinated effective January 18, 2022.
Category : Engineering and Technology
Subcategory : Product Dev Management
Experience : Business Leadership
Full Time / Part Time : Full Time
Posted Date : 2022-01-12
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Equal Employment Opportunity Statement : VMware is an Equal Opportunity Employer and Prohibits Discrimination and Harassment of Any Kind : VMware is committed to the principle of equal employment opportunity for all employees and to providing employees with a work environment free of discrimination and harassment.
All employment decisions at VMware are based on business needs, job requirements and individual qualifications, without regard to race, color, religion or belief, national, social or ethnic origin, sex (including pregnancy), age, physical, mental or sensory disability, HIV Status, sexual orientation, gender identity and / or expression, marital, civil union or domestic partnership status, past or present military service, family medical history or genetic information, family or parental status, or any other status protected by the laws or regulations in the locations where we operate.
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Vmware will provide reasonable accommodation to employees who have protected disabilities consistent with local law.
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