Senior E / E & Semiconductor Engineer - Design Verification Engineer-076750
Description
Position- Mixed Signal DV Engineer
Location- Sunnyvale CA - Onsite role
Job description :
We are seeking Mixed signal Design Verification Engineer who is proficient in system verilog real number modeling and experience with UVM.
Proficient in debug skills and experienced with gate level parasitic annotated simulations. Candidate should be available to work during the US work hours.
Key responsibilities :
- System verilog real number modeling
- Writing regression tests for analog behavioral model verification
- Generating randomized vectors for analog behavioral model verification
- Developing checker & writing assertions.
Required Skills :
- Proficient in system verilog real number modeling
- Familiarity with writing regression tests for analog behavioral model verification
- Hands on experience with UVM
- Familiarity with generating randomized vectors for analog behavioral model verification.
- Familiar with developing checker & writing assertions.
- This is running mixed signal - DMS simulations and developing system verilog and EEnet based analog models
Life at Capgemini
Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer :
- Flexible work
- Healthcare including dental, vision, mental health, and well-being programs
- Financial well-being programs such as 401(k) and Employee Share Ownership Plan
- Paid time off and paid holidays
- Paid parental leave
- Family building benefits like adoption assistance, surrogacy, and cryopreservation
- Social well-being benefits like subsidized back-up child / elder care and tutoring
- Mentoring, coaching and learning programs
- Employee Resource Groups
- Disaster Relief
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