Design Verification Engineer - System Verilog and UVM

ASD Global
Azusa, CA, United States
Full-time
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Required : Bachelor's degree requiredMinimum of 5yrs writing SystemVerilog and UVM as a primary job functionExperience with verification of designs written in VHDLExperience with Linux command line workflowsExperience writing TCL to control verification toolsDemonstrated ability in root-cause analysis of test failuresExperience working closely with RTL designers to collaboratively resolve verification test failuresExperience with Git SCM using LFS and SubmodulesDesired : 10yrs writing SystemVerilog and UVM as a primary job functionExperience creating prediction models from functional requirements documentation using SystemVerilog or SystemCExperience with DPI based simulator interaction for stimulus and predictionProficiency scripting in either Perl or Python for parsing and manipulating text filesExperience with Questa Sim and VisualizerExperience with the UVM-Framework workflowExperience writing split Class / xRTL BFMs for use with both simulation and Co-Emulation (Veloce experience preferred)Experience writing and maintaining Verification Plan DocumentsExperience working on USG Contracts and the associated documentation / process expectationsExperience with common interface specifications used in spacecraftExperience verifying designs targeting radiation hardened Virtex FPGAs.

5 days ago
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