Responsibilities
- Receive Specifications from Module Architects / System Engineers review, assess, provide feedback, and develop a digital micro-architecture
- Generate RTL to comply with specifications, both by manual development and automated generation
- Create Cadence schematic database of Digital Blocks via Virtuoso
- System Verilog Verification Simulations of the design by creating Test Benches at block level. Create new Verification tests and utilize existing tests that are to be modified as needed.
Execute both RTL and Gate Simulations.
- Execute Logic Synthesis
- Execute remaining back-end tools Place & Route / Static Timing Analysis, LEC, LINT, CDC
Qualifications :
- System Verilog / Verilog Language and Simulation
- Scripting languages (Python, TCL, UNIX / LINUX, shell, PERL, C / C++)
- Synthesis and Static Timing Analysis
- Strong communication skills to interface with other teams
- BSEE required, MSEE preferred and 12+ years' experience
- Place & Route using Cadence Virtuoso, verifying Database vs Schematics
- System Verilog Assertions and Functional Coverage
- Formal Verification
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