Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them?
Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?
We’re looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.
Description
We are looking for an experienced design verification engineer to join our SoC team at Baidu’s Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive in this highly technical environment.
Your job responsibilities as a Design Verification Engineer will help the team to verify the functionality of Baidu's AI SoC at both block level and SoC level.
You will help on UVM Testbench development, directed / constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.
Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage.
Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.
Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.
Support emulation and silicon bring up debug with your smart ideas to duplicate the problem in simulation.
Qualifications
- Minimum 5 years of experience of UVM based verification on a significantly complex project.
- Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development.
- Advanced knowledge of System Verilog and the UVM methodology.
- Solid verification skills in problem solving, constrained random testing, coverage closure, gate level simulations, X propagation.
- Good practice of one scripting language (Perl, Python, Tcl) no preference.
- SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache).
- Familiar with C / C++.
- Formal Verification (Model Checking, Equivalence Checking).
- Excellent communication skills in both English and Chinese.
Culture Fit :
- Mission alignment : If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
- Self-directed : We work best with people that are driven, motivated, and aspire to greatness.
- Hungry to learn : We are eager to see you learn new skills and grow.
- Team orientation : We work in small, fast-moving teams. We watch out for each other and go after big goals together as a team.
System IP Design Verification Engineer (Staff-SCI)
Select your country or region to find out what content fits your location .Try using different or more general keywords.Find help about consumer storage product at samsung.By submitting this form, you are confirming you agree to share your personal information with Samsung to use for this business r...
Soc Design Verification Engineer
Create verification content including testplans, test bench components, directed and constrained random tests, and functional coverage. Knowledge of high-level verification flow methodology (testplan development, constrained random test generation and debug, coverage analysis and closure). ...
PHY Design Verification Engineer
Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product l...
Sr. Silicon Design Verification Engineer
AMD's Adaptive and Embedded Computing Group (AECG) is seeking Senior Silicon Design Verification Engineer, who can provide technical leadership and contribution on Verification of Network-on-Chip (NoC) and high-speed Memory Controller IPs. The individual will help design, develop, and use simulation...
Design Verification Engineer
If you are a motivated Design Verification Engineer with expertise in PCIe and DDR, and you have a passion for ensuring the highest quality in digital design, we would love to hear from you!. We are seeking a highly skilled Design Verification Engineer with experience in domains such as PCIe and DDR...
Sr. Design Verification Engineers
Electrical or Computer engineering (or similar field). ...
Sr. PHY Design Verification Engineer
Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product l...
Senior Design Verification Engineer
Senior Design Verification Engineer. At least 7+of experience in Design Verification. ...
Senior E/E & Semiconductor Engineer - Design Verification Engineer
Senior E/E & Semiconductor Engineer - Design Verification Engineer-076748. Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. Failure analysis of Register Transfer Level an...
Design Verification Engineer
Develop and execute test-plans for verifying correctness and performance of the design. Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations. ...