Senior/Principal DRAM Design Engineer

Micron
Boise, Idaho, US
Full-time
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Below, you will find a complete breakdown of everything required of potential candidates, as well as how to apply Good luck.

Our vision is to transform how the world uses information to enrich life for all .

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our Opportunity Summary :

As a Senior or Principal Lead DRAM Design Engineer in the Node Development Design group, you will be responsible for the design and development of next-generation DRAM products.

Working closely with process integration, product engineering, and production design teams, you will contribute to the pathfinding of future DRAM nodes and the development chip design required to bring innovative new insights to production on groundbreaking DRAM products.

You will apply a deep understanding of array parasitic, speed / timing bottlenecks, sense amp margin, CMOS gate variability, and characteristics to drive design optimization and innovations that target an outstanding die size, quality, reliability, and power.

Furthermore, as a team leader, you will be responsible for driving the team to accomplish strategic goals, mentoring team members on technical skills, collaborating with partner teams to resolve issues, and communicating technical details to broader teams.

Disclaimer) : While you may not exhibit all of the characteristics / skills listed below today, we are highly interested in a teammate who is motivated to grow in technical breadth and depth.

Suppose you are open to learning while being a valued member of a team of premier engineers. In that case, we are determined to help build upon your existing foundation, while rapidly growing your individual and collaborative skills in this exciting and outstanding opportunity.

  • This position will be a hybrid role located in our Boise, ID office.
  • The seniority level offered will be based on a combination of experience and education.

What’s Encouraged Daily :

  • Assist with overall design, layout, and optimization of memory circuits.
  • Perform circuit simulations using standard industry tools such as SPICE and VERILOG.
  • Assist in the design and development of schematic blocks such as memory array, control logic, address decode, datapath, and internal test logic.
  • Understand the impact of design architecture decisions on overall power, speed, and die size.
  • Optimize design rules for cost, performance, and functionality.
  • Import layout parasitic information into the circuit simulation environment.
  • Interpret device specifications to produce required functionality.
  • Interact with process integration teams to understand semiconductor technology concerns and opportunities.
  • Build solutions and define requirements for circuit operation, DFM is a key focus.
  • Develop strategies to prove innovative new insights through test chip definition and silicon validation.
  • Look for opportunities to drive competitive advantages into our solutions by developing groundbreaking ideas and concepts.
  • Help guide our team of engineers working on related design tasks, including frequent mentor and technical collaboration.
  • Manage performance and development of a team of engineers to accomplish strategic priorities.

How To Qualify :

  • BSEE or MSEE degree from an accredited university.
  • 5+ years of Design Engineering experience, or 8+ years of Product Engineering in the semiconductor industry.
  • Analog circuit design and / or debugging experience.
  • Simulation experience and familiarity with common simulation tools.
  • Solid understanding of semiconductor process, CMOS device physics, and physical parasitics.
  • Strong understanding of array core architectures, circuits, & functions.
  • Strong interpersonal skills with the ability to convey sophisticated technical concepts to peers and management.
  • Comfortable collaborating with less experienced engineers and inspiring their development through coaching and strong communication of strategic priorities.

What Sets You Apart :

  • Have managed a team in the semiconductor industry regarding Engineering.
  • uMATE & wafer bench data gathering experience.
  • Good DFT / DFM understanding with knowledge of PROBE and Backend test flows.
  • Experience with shell scripts and data extraction of production data.
  • Experience and understanding of MFG process flows / Layout / Defect analysis.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind, and help you prepare for the future.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.

To learn more about Micron, please visit micron.com / careers

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