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Sr. ~ Lead FPGA /CPLD Engineer

Jabil Circuit
Chicago, Illinois, US
Full-time

Build your career with Jabil! We challenge and empower you to make most of your talents, working with outstanding colleagues from diverse backgrounds who share your drive and passion to make Jabil grow!

Qualifications, skills, and all relevant experience needed for this role can be found in the full description below.

JOB SUMMARY

Under the guidance of management, develops new engineering design of a basic to moderate complexity. Gathers design requirements and recommends steps to implement basic to moderate reference design, implementation or design modifications of existing products.

Performs and analyzes basic to moderate circuit design, referring more complex issues to management or more senior team members.

Develops subsystem architecture at the direction of a Sr. Engineer or above.

ESSENTIAL DUTIES AND RESPONSIBILITIES

  • Work closely with Hardware, BIOS, BMC, and Firmware teams for CPLD / FPGA design, validation, and maintenance
  • Develop Server / Storage production power on sequence control logic by CPLD / FPGA
  • Implement new technology and design concepts in CPLD / FPGA
  • Design test plans, development specifications, and issue tracking

JOB QUALIFICATIONS

KNOWLEDGE REQUIREMENTS

TECHNICAL KNOWLEDGE & SKILLS

  • 1-5 years of working experience in CPLD / FPGA development
  • Familiar with CPLD / FPGA design and Verilog / VHDL coding
  • Experience in I2C, SPI, UART, and SGPIO protocols
  • Experience in RTL coding and simulation is a plus
  • Building in the area of CPLDs and FPGAs including coding practice, RTL coding standards, using Git, building test benches, etc.
  • Familiar with C language, PFR, and Eclipse.

NON-TECHNICAL KNOWLEDGE & SKILLS

  • Influence others and share best practices.
  • Effectively communicate with good understanding of English.
  • Work as part of a global team.

EDUCATION & EXPERIENCE REQUIREMENTS

  • Electrical Engineering Degree (BSEE / MSEE or equivalent experience)
  • 1+ years experience in CPLD / FPGA design or other key competency
  • Or an equivalent combination of education, training, or experience.

Domestic and international travel is required (within 1 month).

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3 days ago
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