ASIC/FPGA Design Verification Engineer
Title : ASIC / FPGA Design Verification Engineer with UVM Experience
A high number of candidates may make applications for this position, so make sure to send your CV and application through as soon as possible.
Contract Duration : 6 months 1 day
Published : 3 days ago
Responsibilities :
- Create UVM simulation plan from design specification.
- Create or modify UVC, Score Board, Monitor, and test cases.
- Verify until functional coverage and code coverage meet project threshold.
- Document results.
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