Senior Process Integration Engineer

CA Pay Range (Annual) :

$134,400.00 - $249,600.00

At Infinera, your base pay is one part of your total compensation package. Your actual base pay will depend on your skills, qualifications, experience, and location.

This role may be eligible forequity grants,discretionary bonuses,orcommission payments. The amount of these incentives is based on the terms of the Company’s incentive plans, the Company’s financial performance, and / or individual employee job performance.

Infinera also offers paid leave, medical,

dental, and vision coverage, 401(k),

life, and disability insurance to eligible employees.

Supplement No. 1 to Part 740, Title 15)

Senior Process Integration Engineer,

Sunnyvale, CA

In the position of Senior Process Integration Engineer, you will ensure high quality and reliability of InP-based Photonic Integrated Circuit (PIC) products through extensive experiments and data analysis.

You will work with various functional teams to troubleshoot and improve wafer fabrication processes, develop qualification plans for wafer-level process improvements, maintain design files for process test structures, and drive improvements in yield reliability.

Your Key Responsibilities Would Include :

• Manage the quality of PIC wafers based on knowledge of fab processes, device physics, and the analysis of test and reliability surveillance data.
• Troubleshoot and resolve process deviations and test failures through a detailed analysis of test data and process history
• Investigate the impact of design rules on process yields, develop test structures for effective process control
• Initiate and carry out yield improvement activities, from inception through qualification and implementation
• Support next-generation PIC platform development and participate in technology development, transfer, and ramp activities to meet yield, reliability, cost, and device performance goals
• Support Process Engineering to improve process stability and capability

Education & Experience Necessary For Success :

• Understanding of semiconductor processes and device physics
• Understanding of statistical process control methods
• Familiarity with or direct experience in most of the standard III-V process technologies required for wafer fabrication such as epitaxy, wet etching, plasma etching, metal deposition, and photolithography
• Ability to work in a CAD design environment, generate and maintain mask files as well as die level test structure files
• Database interrogation, statistical analysis skills, and design of experiments
• Excellent communications skills and ability to present data, ideas, and recommendations to a diverse audience

Education Required :

B.S. with at least 3 years of work experience. M.S. level or higher in Electrical Engineering, Photonics, Physics, or Materials Science is preferred.

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