Title : ASIC / RTL / SOC Verification Engineer
Duration : Full Time
Location : San Francisco Bay Area
Description
Testbench development System Verilog Universal Methodology ( UVM ), Python, and C tests
Integration / development of C tests / Application Programming Interface ( APIs ) and software build flow and Integration of UVM testbenches
Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements
Continuous integration and / or regression testing setup and debug for simulation at both RTL and Gate Level Netlist
Unified Power Format ( UPF ) power aware simulation / emulation, XProp simulation / regression Test Bench creation and maintenance , Coverage collection and closure
Documentation of tests, testbench, use-cases, exclusions, and status
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