Job Description :
Responsible for Design Verification of complex IP using latest DV methodologies. Develop DV test plan based on the specification, come up with appropriate DV strategy, build test benches / infrastructure, develop test cases to verify the design.
Responsible to debug any RTL / GLS / Silicon failures and work with RTL engineer to get the bugs fixed. Setup and run Power Aware simulation using UPF to verify the power integrity of design.
Achieve 100% coverage. Develop new DV methodologies. Define and execute Formal verification plan to stress the design. Develop driver api in C for use in the subsystem.
Job Requirement :
- 7 + Years of hands on experience in Design Verification (DV) on Complex IP used in subsystems
- Experienced in all latest DV methodologies : Formal Verification, System Verilog / UVM, Power Aware verification using UPF
- Experienced in developing a DV plan based on Functional Specification, building the necessary test bench / infrastructure, developing tests, and verifying design
- Strong debugging skills and expert knowledge of industry standard simulation (e.g. : VCS) and debug tools
Plus :
- Mixed signal simulation
- Proven ability to develop and deploy new DV methodologies
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