Firmware Engineer

Enhanced Staffing
Irvine, CA
Full-time

Firmware Engineer

Qualifications :
  • US Citizen
  • US Citizen
  • Bachelor’s degree or higher in Electrical, Computer or Equivalent engineering
  • 20 years of experience in Verilog or VHDL designs
  • Ability to architect and partition high speed DSP designs
  • Experienced with the Xilinx Zynq Ultrascale+
  • Worked with the Xilinx IP cores including latest (AXI, PCIe, Memory, IO Interface, and others)
  • Understanding the device architectures and tradeoffs in implementing complex algorithms
  • Image processing and Image compression experience (DFT, filtering, cropping, statistical sampling, etc.)
  • Talented in generating engineering documentations (requirements, block diagrams, and ATPs)
  • Aerospace experience is a plus (Focal Plane Electronics, Cryocooler Control Electronics, etc.)
  • Familiar with Microsemi RTAX and ProASIC family is plus
  • Proficient in generating representations and representing the team in design reviews and technical meetings
  • Responsibilities may include, but are not limited to :

    • Interfacing with customer and creating documents and presentation slides to support design and code review and technical meetings
    • Work closely with a team of software, firmware, electrical, and systems engineers to ensure firmware implementations meet the product requirements
    • Participate in all phases of FPGA design flow - from concept to mass production.
    • Develop high-level design requirements and block-level micro-architectures, partition design within FPGA, and create specification documentswith a strong emphasis on creating reusable and maintainable designs
    • Optimize your designs for area, speed, and power to meet system requirements; analyze architectural trade-offs and use of off the shelf IP.
    • Prototype designs on FPGA, focusing on closely emulating the final product functionality
    • Use scripting languages to achieve higher performance and improve productivity through automatio
    • 30+ days ago
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