Principal Design Verification Engineer
Acceler8 Talent has partnered with a well-supported data center acceleration company that is actively searching for a driven Principal Design Verification Engineer.
This company is deeply committed to developing a novel interconnect architecture aimed at resolving congestion challenges within extensively distributed systems.
Their recent successful completion of a significant Series B funding round serves as a strong indicator of their growth and potential.
The company's founding members bring substantial expertise from distinguished hardware and technology enterprises. Notably, their primary investor boasts an admirable track record of nurturing early-stage startups into prosperous and thriving enterprises.
They are currently seeking an engineer with a high level of expertise with SmartNIC and or Switch Verification , PCIe Serdes / PHY , or Ethernet Serdes / PHY .
If you are located in the San Francisco Bay Area , Austin , TX, Raleigh, NC , or Boston, MA , area this company is offering a fully remote position.
Requirements
- Proven industry experience with CXL and or PCIe
- Industry experience with Ethernet.
- Experience with FPGA design flow / verification is a strong advantage.
- Deep experience with full chip verification and infrastructure development.
- Strong current knowledge of UVM constructs, components, and practices.
- Expert knowledge of SystemVerilog, as well as Python or other scripting languages.
- Experience with C / C++ and general software engineering principles is highly desirable.
- Minimum BSEE / CE + 10 years or MSEE / CE + 5 years experience.
- Proven track record of design execution and quality on products which have shipped in high-volume.
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