Physical and Digital Circuit Design Engineer (6200-1045)

Physical and Digital Circuit Design Engineer (6200-1045)

Job Title : Physical Design Engineer and Digital Circuit Design Engineer

A variety of soft skills and experience may be required for the following role Please ensure you check the overview below carefully.

Department : Hardware Engineering (US)

Location : Location

Job Description

The Core Technology team at Achronix owns the reconfigurable fabric (look-up tables, routing, configuration memory, carry chains, register files, multipliers, etc.

for our company’s FPGAs. Members of our team participate in all phases of the FPGA product-development cycle, from architecture conception to circuit design and implementation to high-volume manufacturing.

New employees will have the opportunity to contribute to all of these phases and work with the world’s most advanced process technology.

Why Join Us?

• Impact Your work will be at the core of products that revolutionize industries.
• Innovation Immerse yourself in an environment that celebrates breakthroughs and encourages out-of-the-box thinking.
• Growth Advance your skills with continuous learning opportunities and career development.

Ready to be a cornerstone in the edifice of technological progress? Apply now and carve your legacy in silicon!

Job Responsibilities

As a Physical Design Engineer and Digital Circuit Design Engineer, you will be a mastermind behind the physical manifestation of cutting-edge semiconductor designs.

You will transform abstract concepts into tangible, high-performance hardware that powers the next generation of devices.

Primary Job Responsibilities

• Lead the RTL-to-GDS journey, sculpting the landscape of chips that will power tomorrow's innovations.
• Tackle complex timing and power challenges, ensuring our designs not only meet but exceed performance expectations.
• Conduct rigorous physical verification to ensure flawless functionality before the grand tape-out.
• Set up state-of-the-art flows and automate processes for peak efficiency.
• Work alongside a team of brilliant minds, integrating custom logic and IP.
• Get involved in semi-custom digital circuit design, floor-planning, track-planning and gain a better understanding of circuit and layout design concepts.

Preferred Skills

• Proficiency in using industry standard tools such as Fusion Compiler, IC Compiler II, Design Compiler, PrimeTime, Redhawk, Calibre, ICV, etc.
• Experience with floorplanning, placement, routing, timing closure, and power optimization.
• Experience with CTS optimizations, special clock routing rules, and cell placement related to jitter clock of PLL.
• Ability to perform physical verification checks such as DRC, LVS, ERC, etc., and debug issues.
• Understanding of low-power design techniques such as power gating, voltage islands, clock gating, etc.
• Understanding of device physics, basic understanding of CMOS design, and circuit simulations using HSPICE or equivalent circuit simulators.
• Ability to design and optimize custom / semi-custom CMOS digital circuits.
• Proficient in a scripting language such as Tcl, Perl, Python, etc.
• Good communication and teamwork skills.

Education and Experience

• BS / MS in Electrical Engineering or Computer Science with 3-12 years experience.
• Track record of successful tape-outs and working knowledge of advanced FinFet technology nodes (16nm / 7nm / 3nm) and beyond.
• Proficient in EDA tools, scripting languages, and methodologies, orchestrating the physical design with precision and creativity.

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