Senior FPGA Design Engineer

Introduction

ASML US, including its affiliates and subsidiaries, bring together the most creative minds in science and technology to develop lithography machines that are key to producing faster, cheaper, more energy-efficient microchips.

We design, develop, integrate, market, and service these advanced machines, which enable our customers - the world's leading chipmakers - to reduce the size and increase the functionality of their microchips, which in turn leads to smaller, more powerful consumer electronics.

Our headquarters are in Veldhoven, Netherlands, and we have 18 office locations around the United States including main offices in Chandler, Arizona, San Jose and San Diego, California, Wilton, Connecticut, and Hillsboro, Oregon.

Job Mission

As Senior FPGA verification engineer, you will participate in a cross-functional and collaborative team to ensure functionality of the target FPGA design while developing a robust verification environment for ASML's EUV Source and global FPGA community.

This position requires access to controlled technology, as defined in the Export Administration Regulations (15 C.F.R.

730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work.

Business demands may require the Company to proceed with candidates who are immediately eligible to access controlled technology.

You must be work authorized in the United States without the need for employer sponsorship.

Job Description

• Key contributor for the FPGA verification plan and major infrastructure development for a complex FPGA network.
• Collaborate with FPGA architects, verification lead, design and test engineers to verify RTL design, ensuring adequate coverage and maximizing reusability.
• Develop verification plans, test benches and UVM components to ensure code / functional coverage from block to chip-to-chip level simulation.
• Perform requirement traceability via Test Performance Specification (TPS) and capturing results in Test Acceptance Report (TAR).
• Contribute to continuous improvement and optimization of the UVM structure.
• Other duties as assigned.
• Job description subject to change at any time.

Education and Experience

• BS or higher in EE, CS or related engineering fields.
• Minimum of six (6) years' experience in FPGA targeted verification.
• Highly proficient in System Verilog based UVM with demonstrated experience creating UVM agents and components (predictors, scoreboard, etc.) without templates.
• Familiar with VHDL syntax and use for RTL design.
• Familiar with Xilinx SoC / Altera FPGA target verification.
• Experience using Siemens UVM framework and associated tooling environments (Questa Sim).
• Proficiency with Python a plus.
• Familiar with revision control system and platforms such as Git and Gitbucket.

Skills & Competencies

• Ability to learn and apply new information and / or skills.
• Demonstrated creative problem solving for complex issues.
• Can read and interpret data, information, and documents.
• Track record of completing assignments with attention to detail and high degree of accuracy.
• Proven ability to perform effectively in a demanding environment, within provided timelines, and with changing workloads.
• Results driven; exhibits ownership and accountability.
• Work independently or as part of a team and follow through on assignments with minimal supervision.
• Strong professional communication which is clear and concise.
• Ability to establish and maintain cooperative working relationships with co-workers.

Other Information

This position is located on-site in San Diego, California. It works on a hybrid schedule, 3 days onsite / 2 days remote.

It also requires onsite presence to attend in-person work-related events, trainings and meetings and to further ensure teamwork, collaboration and innovation.

Routinely required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch.

Occasionally required to move around the campus.

• Occasionally lift and / or move up to 20 pounds.
• Specific vision abilities required by this job include close vision, color vision, peripheral vision, depth perception, and ability to adjust focus.

EOE AA

M / F / Veteran / Disability

Potential candidates will meet the education and experience requirements provided on the above job description and excel in completing the listed responsibilities for this role.

All candidates receiving an offer of employment must successfully complete a background check and any other tests that may be required.

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Diversity and inclusion

ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity.

We recognize that diversity and inclusion is a driving force in the success of our company.

Request an Accommodation

ASML provides reasonable accommodations to applicants for ASML employment and ASML employees with disabilities. An accommodation is a change in work rules, facilities, or conditions which enable an individual with a disability to apply for a job, perform the essential functions of a job, and / or enjoy equal access to the benefits and privileges of employment.

If you are in need of an accommodation to complete an application, participate in an interview, or otherwise participate in the employee pre-selection process, please send an email to USHRServiceCenter@asml.

com to initiate the company's reasonable accommodation process.

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