Senior DRAM Module Design Engineer

SMART
Newark, CA, US
$148K-$175K a year
Full-time

Overview

SMART is seeking a Senior DRAM Hardware Design Engineer responsible for the development of DIMM and custom memory module designs for leading-edge, high-performance server and embedded applications.

This job provides the opportunity to work closely with the customers, engineering, manufacturing and test groups. The job requires analytical problem-solving skill, ability to work independently and on multiple projects.

Responsibilities

  • Perform Hardware Design Engineering activities such as writing design specifications, schematic capture, component selection, working with Layout Engineers for PCB design, and post-layout SI / PI simulation.
  • Validate designs in the lab to ensure design requirements are met.
  • Perform research as required to define, specify, and develop products.
  • Root-cause analysis to identify issues raised by testing or customer returns.
  • Make recommendations for product / process corrections and improvements
  • Develop positive relationships with other engineering, manufacturing, and test groups.

Qualifications

  • BS or MS in electrical engineering or equivalent
  • 10+ years of high-speed memory interface related professional work experience
  • Strong knowledge of electrical engineering, analog / digital circuit, and power electronics fundamentals
  • Schematic capture using Orcad CIS and experience working with a centralized part library and design process
  • Familiar with Cadence PCB layout tool and experience completing design release and working with layout engineers to determine component placement, routing topology and design constraints.
  • Working knowledge of standard methodologies in PCB design, including stack up and impedance control.
  • Experience post-layout simulation that includes Signal Integrity (SI) and timing analysis and Power Integrity (PI) simulation.
  • Ability to use high-speed oscilloscope and logic analyzer to perform bring-up and make Design Validation Testing (DVT) measurements, and for troubleshooting.
  • Working knowledge of JEDEC DDR3 / DDR4 / DDR5 standards.
  • Communicate effectively verbally and in writing with internal team members as well as customers with logical thinking and a proactive problem solving mindset.

Location

Newark, CA

Travel

No travel required

Compensation & Benefits

The base pay range that the Company reasonably expects to pay for this position in Newark, CA is $148,000 - $175,000; the pay ultimately offered may vary based on business considerations, including job-related knowledge, skills, experience, and education.

The position is bonus-eligible, and there are medical, dental, and vision benefits available. There is a 401k saving plan and other benefits, such as Paid Time Off, Life Insurance, and an Employee Assistance Plan.

Diversity and Inclusion Statement

SGH, together with its affiliates, is committed to creating a diverse environment that embraces differences and fosters inclusion.

Equal Opportunity Statement

We are an Affirmative Action / Equal Opportunity Employer and strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, national origin, race, ethnicity, creed, gender, disability, veteran status, or any other characteristic protected by law.

30+ days ago
Related jobs
Promoted
Winbond Electronics Corporation America
San Jose, California

Collaborate with layout designers to support and guide product engineers in testing and debugging design tasks. Define test modes to facilitate easy debugging from process, design, and product engineering perspectives, while also addressing production concerns. Participate in defining chip architect...

Promoted
MediaTek
San Jose, California

MediaTek’s advanced Memory Design team in San Jose is looking for a senior memory design engineer to define and architect memory circuits for high performance compute ASICs targeting Cloud AI, Data Center Networking, Automotive and other Enterprise ASIC applications as well as edge AI Machine Learni...

Promoted
Trilyon, Inc.
San Jose, California

Collaborate with thermal engineers to design and implement cooling solutions. Provide technical design guidance and mentoring for junior engineers. Bachelor’s degree in mechanical engineering or equivalent and 8-12 years of EMS design experience. Design and deliver next generation chassis and cards ...

Promoted
Nvidia Corporation
Santa Clara, California

NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world’s leading SoC's and GPU's. Collaborate with architects, verification engineers, software engineers, and physical design engineers to accomplish your goals. A deep understanding of ASIC design flow includin...

Promoted
Ampro ADLINK Technology, Inc.
San Jose, California

Strong understanding of reliability requirements and the impact of engineering design choices on the production process. Lead all aspects of schematic design, including reviewing layouts, exporting Bill of Materials (BOM), conducting prototype bring-up, and troubleshooting issues throughout the deve...

Promoted
Pivotal
Palo Alto, California

As the Senior Motor Design Engineer, you will work with a small team of engineers and technicians that are responsible for the design, manufacturing, and testing of subsystems within the eVTOL aircraft Helix specifically around the motor and propulsion system. Performs all aspects of vehicle design ...

Promoted
Skyworks Solutions, Inc.
San Jose, California

Work closely with a team of EM Design Engineers, Lab Technicians, Validation/Optimization Engineers, Test Engineers and Package Engineers to tackle complex cellular RF front end issues. Selected team member for the RF SiP Module Design Engineer position can work at various location of Skyworks, San ...

Promoted
CV Library
San Jose, California

As a senior ASIC Physical Design Engineer, you will work closely with other digital designers and mixed signal designers to develop the next generation of mining ASIC. Our organization operates as a flat meritocracy; this role’s title is ASIC Physical Design Engineer, but other companies might call ...

Promoted
Apple Inc.
Cupertino, California

Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient / low power design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integ...

Promoted
Samsung Semiconductor
San Jose, California

The DRAM Design Lab (DDL) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash. Come join the team that is designing HBM product, developing DRAM architecture, co-working head office and managing customer in all stages of design. Collabor...