Acceler8 Talent has recently partnered with a company that is redefining AI hardware, focusing on maximizing performance for large language models (LLMs) like GPT.
With a commitment to cost efficiency and optimizing performance-per-dollar, their technology offers competitive latency and low-level hardware control.
Their scalable hardware enables faster model development and accessibility for researchers and startups.
Founded by two previous leaders of a FAANG company, they are leading the charge as the compute platform for AGI, crafting comprehensive solutions from silicon to systems.
They are actively looking for a Physical Design Engineer
Responsibilities :
- Drive their silicon and physical design methodology, ensuring scalability across various design levels.
- Take ownership of entire subsystems or subsets and / or chip-level physical design tasks, including floor-planning, placement, routing, timing closure, and verification.
- Lead reviews and progress reporting, focusing on key metrics to achieve silicon milestones like design freeze and tapeout.
- Collaborate closely with design, DFT, and other physical design stakeholders to deliver top-tier performance, power, and area results.
- Coordinate with design services partners and third-party vendors for block-level and chip-level
Requirements :
- Proven experience in guiding physical design from RTL to silicon for subsystems and / or top-level functions in ASICs and SOCs.
- Demonstrated expertise in floorplanning, place and route, clock tree insertion, timing analysis, physical verification, and electrical sign-off.
- Project experience collaborating with design, verification, and DFT teams to optimize designs for performance, power, and area.
- Experience working with third-party design services partners to take designs from initial floor plan to sign-off and tapeout is desirable.
If interested in joining them please apply here or reach out to Jwhitcomb@acceler8talent.com
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