Technical Staff Engineer - Validation (System Design)

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Job Description :

The Candidate will be an expert with 32Gbps SERDES (Serializer / Deserializaer) based protocols, and must possess recent work experience with Gigabit Ethernet (10 / 25 / 40 / 50 / 100 / 200 / 400G) and PCIe Rev.

3 / 4 / 5 protocol; and be able to use FPGAs to create systems level designs to bring up and debug such systems in the lab.

• Architecture definition and FPGA design creation utilizing all hardware features and IP cores targeted to existing and future Microchip products.
• System and FPGA design must exercise all the use models targeted for each product mimicking end applications in a customer setting.
• Develop high level system and product level validation plans for new and existing silicon products and project, execute per plan.

Review dependencies, estimate effort and identify and communicate risk.

• Understand hardware architectures, define use models and execute / oversee system level design implementations required to utilize the silicon features.
• Be not only an effective contributor but also the technical expert related to protocols using high speed serial interfaces in a cross-functional team-oriented environment.
• Write high quality code in Verilog, VHDL and C code. Maintain existing code. Support regression and re-use.
• Learn new system designs and validation methodologies. Understand FPGA architectures.
• Act as the authoritative expert in knowledge domain area(s), be able to mentor senior and junior engineers and provide technical guidance.

This involves assigning and monitoring tasks of employees and contractors.

• Collaborate with cross-functional managers / teams to identify and resolve inter-dependencies.
• Define and improve process followed in the department; follow quality metrics and assess per project.
• Must be willing to take regular late night or early morning calls to interface with the engineering team in India Standard Time zone, when and if required.

Requirements / Qualifications :

Minimum Qualifications :

BSEE / BSCS or equivalent with 12+ years of experience or MSEE / MSCS with 10+ years of experience.

Knowledge of FPGA architectures is a must

Possess an in-depth understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios

Strong technical background in FPGA prototype emulation, and debug

Strong technical background in silicon validation, failure analysis and debug

Excellent Board level debug capabilities in lab environment : hands-on troubleshooting skills for digital logic and analog circuit on PCB’s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.

g. Synopsys Identify, Xilinx Chipscope, Altera Signalscope, Lattice Reveal)

Design with RTL coding in Verilog and VHDL is a must

Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools

Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB

Familiarity with the bring up and on-board debug of 32Gbps SERDES

Hands-on systems level design and debug experience with following high-speed serial communications protocols (must : PHY, PCS and Data link layer of the OSI protocol stack;

desirable : transaction and upper layers of the OSI protocol) :

Protocol Testing at UNH for various IEEE Clauses pertaining to

Layer 1 / 2 / 3 of Gigabit Etherent

PCIe Gen3 / 4 / 5

Experience with the Compliance Tests :

Protocol Testing at UNH for various IEEE Clauses pertaining to Layer 1 / 2 / 3

Protocol Testing, PCI-CV Testing, PHY Testing.

Experience with the Lab Equipment

Spirent Test Center or equivalent Traffic Generators and Checkers

PCIe Analyzer & PCIe Exerciser

Strong commitment to quality and customer satisfaction

Excellent verbal and written communication skills in English

Able to travel 0-2 times annually if required.

Preferred qualifications

Familiarity with any high speed SERDES controllers that make use of 32Gbps PCS, PMA :

• Ethernet 1, 2.5, 5, 10, 25, 40, 50, 100, 200, 400 Gbps, including familiarity with (U)S(X)GMII
• Interlaken (4.25 to 412.5 Gbps)
• OTN OTUx (2.66 to 131 Gbps), or SONET / SDH OC3 / 12 / 48 / 192

E,X,XGS,NG)-PON or 100G-EPON

• Video interfaces SDI-SD / HD / 3GHD and SDI (5.94, 11.88Gbps), Displayport (6.48 to 25.92Gbps), HDMI (3.96 to 42.66 Gbps)
• JESD204C (6.375 to 32 Gbps)

Design and debug experience for any of the below high-speed serial communications protocols is a plus, but not necessary :

• Hybrid Memory Cube
• CPRI Rate 1 to 10+
• Serial Rapid IO 4.1
• USB 3.0
• SATA I, II, III
• Fiber Channel
• CoaXpress

C, C++ or object-oriented programming skills is desirable Knowledge and experience in embedded firmware development is desirable Good understanding of embedded firmware / software development process is desirable Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming is desirable Knowledge of PERL / TCL scripting is desirable

Percentage of time spent :

Documentation 15%

Design Creation & Verification 25%

Lab Bringup & Debug 60%

Essential Physical Functions and Working Conditions :

50 % work in front of computer

50% work in the lab

Travel Time : 0% - 25%

0% - 25%

Physical Attributes :

Feeling, Handling, Hearing, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements :

70% sitting, 15% standing, 15% walking; 100% in doors; Usual business hours.

Pay Range :

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments.

In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature.

Find more information about all our benefits at the link below : The annual base salary range for this position, which could be performed in California, is $75,000 - $232,000.*

Range is dependent on numerous factors including job location, skills and experience.

Microchip Technology Inc is an equal opportunity / affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to the and the . Please also refer to the .