Need submission details for FPGA Verification Engineer, Santa Cl

Dear Partner, Good Morning ,Greetings from Nukasani group Inc !, We have below urgent long term contract project immediately available for FPGA Verification Engineer, Santa Clara, CA, Onsite need submissions you please review the below role, if you are available, could you please send me updated word resume, and below candidate submission format details, immediately. If you are not available, any referrals would be greatly appreciated. Interviews are in progress, urgent response is appreciated. Looking forward for your immediate response and working with you. Candidate Submission Format - needed from youFull Legal NamePersonal Cell No ( Not google phone number)Email IdSkype IdInterview AvailabilityAvailability to start, if selectedCurrent LocationOpen to RelocateWork AuthorizationTotal Relevant ExperienceEducation. / Year of graduationUniversity Name, LocationLast 4 digits of SSNCountry of BirthContractor Type : mm / dd Home Zip Code Assigned Job Details Job Title : FPGA Verification EngineerLocation : Santa Clara, CA, OnsiteRate : Best competitive rate Position Overview We are seeking a highly skilled and motivated FPGA Verification Engineer to join our clients advanced engineering team in Santa Clara, CA. The ideal candidate will bring strong expertise inFPGA verification, SystemVerilog, and UVM, working hands-on to ensure functional correctness, performance, and reliability of complex FPGA designs. This is a full-time onsite position (5 days per week) offering a dynamic and collaborative work environment where youll play a key role in delivering high-quality FPGA-based solutions. Key Responsibilities Develop and execute comprehensive verification plans for complex FPGA designs. Create, enhance, and maintain test benches using SystemVerilog andUVM methodologies. Write and debug test cases to validate functional, performance, and corner-case scenarios. Conduct code coverage and functional coverage analysis to ensure verification completeness. Identify, debug, and resolve design and verification issues in collaboration with FPGA design engineers. Document verification results and provide detailed, actionable reports. Participate in design and code reviews to contribute to overall verification strategy and product quality. Stay current with emerging verification methodologies, tools, and best practices. Required Skills & Experience 8+ years of professional experience in FPGA verification. 5+ years of hands-on experience withUVM and SystemVerilog. Strong understanding of FPGA architectures, design principles, and verification flows. Experience with industry-standard verification tools (e.g., QuestaSim,Synopsys VCS, Vivado Simulator Expertise in code and functional coverage analysis. Strong debugging, analytical, and problem-solving skills. Excellent written and verbal communication skills for effective collaboration with cross-functional teams. Additional Preferred Skills Experience with scripting languages such as Python or Perl for automation and test management. Familiarity with hardware description languages (VHDL, Verilog Knowledge of FPGA design toolchains and simulation environments. Education Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related technical field.