Acceler8 Talent is partnered with an AIoT Acceleration company that recently closed its series C funding. The company, founded in 2019, has secured over $235 million, completed two successful tapeouts, and established bases worldwide.
They've introduced two devices for developers, offering a single-chip solution for AI / ML edge processing, wireless connectivity, and substantial memory.
The company is actively seeking a qualified DFT Manager to lead the creation, maintenance, and execution of tests for a multi-processor SoC.
The role also involves supervising a global team of engineers.
Responsibilities
- This engineer must have strong experience with Mentor Tessent.
- Define & document DFT requirements / Specifications for IP / Block and Chip level
- Execute DFT Lint to identify scan DRC violations and resolution
- Plan and Insert MBIST and memory repair
- Generate and port IJTAG ICL / PDL and STIL patterns for MBIST, ATPG, and JTAG tests
Requirements
- 10+ years of proven DFT execution experience on mixed-signal SoC with first-pass silicon success
- Expertise in using Cadence for scan stitching and Mentor Tessent tool suite for DFT implementation
- Hands-on hierarchical DFT flow experience from RTL to netlist
- Experience in inserting EDT, wrapper cells and OCC
- Experience in analyzing DFT DRC violations and fault coverage analysis
If you would like to learn more about this company feel free to drop me a message or email me at Jwhitcomb@acceler8talent.com
DFT Manager
Define & document DFT requirements/Specifications for IP/Block and Chip level. Execute DFT Lint to identify scan DRC violations and resolution. DFT execution experience on mixed-signal SoC with first-pass silicon success. Expertise in using Cadence for scan stitching and Mentor Tessent tool suite fo...
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