Principal ASIC Design Engineer

Description

Synaptics is leading the charge in AI at the Edge, bringing AI closer to end users and transforming how we engage with intelligent connected devices, whether at home, at work, or on the move. As the go-to partner for the world’s most forward-thinking product innovators, Synaptics powers the future with its cutting-edge Synaptics Astra™ AI-Native embedded compute, Veros™ wireless connectivity, and multimodal sensing solutions. We’re making the digital experience smarter, faster, more intuitive, secure, and seamless. From touch, display, and biometrics to AI-driven wireless connectivity, video, vision, audio, speech, and security processing, Synaptics is the force behind the next generation of technology enhancing how we live, work, and play.

Overview

Synaptics is looking for a highly experienced Principal ASIC Design Engineer to provide technical leadership and architectural expertise.  This role requires deep knowledge of digital design methodologies, strong problem-solving skills, and the ability to guide cross-functional teams through complex design and verification challenges. This role will play a key role in driving innovation, ensuring design quality, and influencing the strategic direction of ASIC development. This position reports to the Sr. Director, ASIC Design.

The typical base pay range for this position is USD $182,000 - $286,000 per year. Individual pay is determined by many factors including work location, job-related skills, experience, and relevant education or training. This position is also eligible for a discretionary annual performance bonus, equity, and other benefits. Note that compensation listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

Responsibilities & Competencies

Job Duties

• Lead the architecture, design, and implementation of complex ASICs from concept through production
• Define design specifications, micro-architecture, and system-level interfaces in collaboration with system architects, firmware / software teams, and hardware engineers
• Responsible for SoC-level integration of high-speed interface IPs (PCIe, USB, HDMI, MIPI) and end-to-end support through pre-silicon verification and post-silicon bring-up
• Drive tradeoff analyses across power, performance, area, and cost (PPA) to ensure optimal design solutions
• Oversee RTL coding, synthesis, linting, and static timing analysis, ensuring high-quality, reusable, and scalable designs
• Guide verification planning and methodologies, collaborating closely with the verification team to ensure functional correctness and coverage closure
• Partner with physical design teams to resolve timing, floorplanning, and power optimization challenges
• Serve as the technical point of escalation for complex design / debug issues, providing hands-on problem-solving support
• Evaluate and adopt advanced design methodologies, tools, and flows to improve efficiency and quality
• Mentor junior engineers, setting best practices in coding standards, design reviews, and documentation
• Collaborate with product and program management to align design activities with project schedules, milestones, and deliverables
• Contribute to customer and partner engagements, providing technical expertise and influencing product direction

Competencies

Qualifications (Requirements)

Belief in Diversity

Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information.