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Silicon Design Verification Engineer.
Silicon Design Verification Engineer.Advanced Micro Devices • San Jose, CA, United States
Silicon Design Verification Engineer.

Silicon Design Verification Engineer.

Advanced Micro Devices • San Jose, CA, United States
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WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE :

As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD / Xilinx programmable devices.

THE PERSON :

You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites / time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES :

  • Collaborate with architects, hardware and firmware engineers to understand the new features to be verified
  • Take ownership of block level verification tasks
  • Define test plans, test benches, and tests using System Verilog and UVM
  • Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes
  • Review functional and code coverage metrics to meet the coverage requirements
  • Develop and improve existing verification flows and environments

PREFERRED EXPERIENCE :

  • Strong understanding of computer architecture and logic design
  • Knowledge of Verilog, system Verilog and UVM is a must
  • Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification
  • Working knowledge of C / C++ and Assembly programming languages
  • Exposure to scripting (python preferred) for post-processing and automation
  • Experience with gate level simulation, power and reset verification
  • ACADEMIC CREDENTIALS :

  • Bachelors or Masters degree in computer engineering / Electrical Engineering or a related field
  • LOCATION : San Jose, CA

    #LI-DW1

    #LI-HYBRID

    Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

    #J-18808-Ljbffr

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    Design Verification Engineer • San Jose, CA, United States

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