Senior Verification EngineerRetym, Inc • Austin, TX, US
Senior Verification Engineer
Retym, Inc • Austin, TX, US
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job_description.job_card.job_descriptionPlan and perform the verification of digital design blocks according to the design specification and interacting with design engineers. Build verification environments using SystemVerilog and UVM. Identify and write all types of coverage measures for corner-cases. Debug the functionality with design engineers. Perform coverage collection and follow the metrices to close the full functionality.
Overview
For an exciting well-funded start-up developing leading edge technology in high-speed communications, we are looking for a Senior Verification Engineer to drive RTL design verification across various design aspects.
Requirements
- 10+ years of experience – a must
- Performed at last 2 or more full block / system verification cycles.
- In depth knowledge in VLSI verification flow, languages and concepts.
- Experience in data path or data protocols, specifically Ethernet - preferred
- Verification using one of the known methodologies (eRM, UVM).
Responsibilities
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