IC Layout Designer
TCWGlobalCupertino, CA, United Statesjob_description.job_card.1_day_ago
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job_description.job_card.job_descriptionPerform detailed transistor-level layout of RF and analog circuit blocks (e.g., LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC / DAC, baseband filters, bandgap / bias / LDO) Complete block-level layout through the full verification flow, including extraction, DRC, LVS, and DFM checks Collaborate with designers on block-level floorplanning and architecture integration Conduct layout reviews for power / ground routing, electromigration, signal path integrity, differential / IQ matching, and signal coupling Support the research, design, and production of next-generation wireless technologies in advanced CMOS nodes BS degree with 7+ years of relevant industry experience Hands-on FinFET technology expertise — FinFETs are an advanced type of transistor used in modern chips where the channel is shaped like a vertical “fin,” allowing better control of current, higher performance, and smaller sizes. Experience here means understanding layout challenges specific to these nodes, such as parasitics, matching, and multi-patterning. Strong knowledge of layout verification flows (DRC, LVS, extraction) and design for manufacturability Solid understanding of RC delay, electromigration, coupling, and advanced process effects (LOD, WPE, etc.) Proficiency in CADENCE layout tools and interpretation of CALIBRE checks (DRC, ERC, LVS) Excellent communication skills and ability to collaborate across design and verification teams Experience in custom RF / analog layout for radio transceivers, with extensive knowledge of deep sub-micron CMOS Familiarity with layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing Experience at 7nm FinFET or smaller nodes Scripting skills in PERL or SKILL
IC Layout Designer
Location : Cupertino, CA (Hybrid-
- Local candidates only)
Payrate : $67–$78.35 / hr
Duration : 7-month assignment (possibility of extension)
Hours : Full-time 40 hours / week
Summary
Do you want to help shape the future of wireless technologies that power products used by hundreds of millions of people worldwide? We’re looking for a IC Layout Designer to join our client’s world-class vertically integrated engineering team. In this role, you’ll work closely with circuit designers to layout and verify custom RF and analog IP that will be integrated into state-of-the-art SoC products.
You’ll bring deep technical expertise in advanced CMOS processes, precision in layout design, and a collaborative spirit to partner with cross-functional teams. If you thrive on solving complex challenges in high-performance analog and RF design, this is your opportunity to make an impact at scale.
What You’ll Do
What You Bring
Bonus Points If You Have
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Layout Designer • Cupertino, CA, United States
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