- 6 to 10 years of experience in DV.
- Testbench development System Verilog Universal Methodology ( UVM ), Python, and C tests
- Integration / development of C tests / Application Programming Interface ( APIs ) and software build flow.
- Good experience with Python.
- Integration of UVM testbenches.
- Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements.
- Continuous integration and / or regression testing setup and debug for simulation at both RTL and Gate Level Netlist.
- Unified Power Format ( UPF ) power aware simulation / emulation.
- XProp simulation / regression TestBench creation and maintenance.
- Coverage collection and closure.
- Documentation of tests, testbench, use-cases, exclusions, and status.
Senior Staff Design Verification Engineer
A company is looking for a Senior Staff Design Verification Engineer to join their team. ...
Design Verification Engineer
Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements. ...
Senior Design Verification Engineer
A company is looking for a Senior Design Verification Engineer to join their team. ...
Sr. Design Verification Engineer (Silicon Engineering)
DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING). We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). Design Verifica...
Senior Design Verification Engineer
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Lead FPGA/ASIC designs, including multi-FPGA/ASIC programs and teams with design and verification engineers, and manage team execution to meet program milestones. Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers ...
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Our Client, a worldwide technology corporation, is seeking an experienced Hardware Design Verification Engineer for an 18-month contract assignment located hybrid/onsite in Redmond, WA. As a Hardware Design Verification Engineer on this Team, you will be supporting the next generation version of AI ...
ASIC and/or FPGA Design & Verification Engineers (Entry-Level, Associate, Experienced) WA
Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers at Entry Level, Associate and Experienced levels to join us as part of our Boeing Electronic Products team at the heart of Boeing’s products; ASICs and FPGAs in Tu...