A seasoned Design Verification Engineer with over 10 years of experience to join their team in San Jose.
The ideal candidate will have extensive expertise in PCle protocol and hands-on experience in ASIC / FPGA design verification.
Responsibilities include developing and executing test plans, creating and maintaining verification environments using System Verilog / UVM, and debugging complex design issues.
The role demands proficiency in scripting languages (Python, Perl) and strong analytical and problem-solving skills.
Familiarity with modern EDA tools and methodologies is essential. Excellent communication and teamwork abilities are required to collaborate effectively with cross-functional teams.
Design Verification Engineer - Neural Engine
Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the Neural Engine work under all specified circumstances. Have strong communication skills combined with good team-oriented approaches to lead the verification ...
Design Verification Engineer
Job Title: Senior Design Verification Engineer. Verification: Experience at all level - Block level - subsystem level. ...
Design Verification Engineer
Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements. ...
Design Verification Engineer
Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth. Engineer will be engaging in UVM verification for a large tech company. Triple Cr...
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Develop and execute test-plans for verifying correctness and performance of the design. Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations. ...
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