Search jobs > San Jose, CA > Design verification
A seasoned Design Verification Engineer with over 10 years of experience to join their team in San Jose.
The ideal candidate will have extensive expertise in PCle protocol and hands-on experience in ASIC / FPGA design verification.
Responsibilities include developing and executing test plans, creating and maintaining verification environments using System Verilog / UVM, and debugging complex design issues.
The role demands proficiency in scripting languages (Python, Perl) and strong analytical and problem-solving skills.
Familiarity with modern EDA tools and methodologies is essential. Excellent communication and teamwork abilities are required to collaborate effectively with cross-functional teams.
Design Verification Engineer - Neural Engine
Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the Neural Engine work under all specified circumstances. Have strong communication skills combined with good team-oriented approaches to lead the verification ...
Design Verification Engineer
Job Title: Senior Design Verification Engineer. Verification: Experience at all level - Block level - subsystem level. ...
Design Verification Engineer
Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements. ...
Design Verification Engineer
Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth. Engineer will be engaging in UVM verification for a large tech company. Triple Cr...
Design Verification Engineer
As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Experience in design verification with UVM and SystemVerilog is a MUST. Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster lev...
Principal Design Verification Engineer
We are seeking experienced Principal Design Verification Engineers with a strong aptitude for working on Emulation Platforms. Utilize coding and problem-solving skills to contribute to the functional verification of designs. Strong academic background in Electrical Engineering (Bachelor's required, ...
Design Verification Engineer
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple’s premier SOCs. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. As part of a very dedicated team you will be at ...
R&D Engineer IC Design Verification
Engineer will be responsible for verification of complex switch designs. Responsibilities will include creating SystemVerilog-based verification environments (testbenches, checkers, transactors) as well as creating and executing testplans for verifications of RTL and gatesim-based designs at both th...
Design Verification Engineer
Develop and execute test-plans for verifying correctness and performance of the design. Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations. ...
Asic Design Verification Engineer
As a verification engineer, your responsibilities will include:. Debug RTL and Gate simulations and work with design engineers to verify fixes. Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup. Debug RTL and Gate simulations and work with design engineers t...