Search jobs > Sunnyvale, CA > Design verification
- 6 to 10 years of experience in DV.
- Testbench development System Verilog Universal Methodology ( UVM ), Python, and C tests
- Integration / development of C tests / Application Programming Interface ( APIs ) and software build flow.
- Integration of UVM testbenches.
- Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements.
- Continuous integration and / or regression testing setup and debug for simulation at both RTL and Gate Level Netlist.
- Unified Power Format ( UPF ) power aware simulation / emulation.
- XProp simulation / regression TestBench creation and maintenance.
- Coverage collection and closure.
- Documentation of tests, testbench, use-cases, exclusions, and status.
Digital Design Verification Engineer
A company is looking for a Staff Digital Design Verification Engineer. ...
Wireless Design Verification Engineer
Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product l...
Design Verification Engineer
Acceler8Talent is seeking a skilled, driven Design Verification Engineer with expertise in designing and verifying large-scale computing and networking semiconductor chips. We are partnered with a company that is looking for talented, experienced verification engineers who can contribute across the ...
Wireless SoC Design Verification Engineer
As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state of the art Wireless SoCs! This position requires someone comfortable with all areas of SoC design verification engineering...
Design Verification Engineer
Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements. ...
Design Verification Engineer
Utilize industry-standard verification methodologies and tools, with a deep understanding of UVM, System Verilog, RTL design, and verification. Principal ASIC/SoC Verification Engineer. As a Principal ASIC/SoC Verification Engineer you'll play a pivotal role in verifying IP for ASIC products, includ...
Design Verification Engineers (SoC-5, PCIe-5)
Job Title: Design Verification Engineers. Role: Design Verification Engineers (SoC-5, PCIe-5). Debug RTL and Gate simulations and work with design engineers to verify fixes. Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup. ...
Principal Design Verification Engineer (contract)
As a Design Verification Engineer, you will be an integral part of our mission to deliver cutting-edge cryptography processors. Work cross functionally to integrate the verification environment into the overall design flow. Own and develop formal and UVM verification methods to ensure the completene...
System IP Design Verification Engineer (Sr. Staff-SCI)
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Senior ASIC Design Verification Engineer
What you’ll be doing: Work with some of the best DSP, system, and software engineers to define verification strategies and execute plans at system or full chip level Build and continuously improve verification infrastructure and methodologies to meet the demands of next generation SoCs Work wi...