Position- Mixed Signal DV Engineer Location- Sunnyvale CA - Onsite role Job description :
We are seeking a Mixed Signal Design Verification Engineer who is proficient in System Verilog real number modeling and has experience with UVM.
Proficient in debug skills and experienced with gate level parasitic annotated simulations. Candidate should be available to work during US work hours.
Key responsibilities :
- System Verilog real number modeling
- Writing regression tests for analog behavioral model verification
- Generating randomized vectors for analog behavioral model verification
- Developing checkers & writing assertions.
Required Skills :
- Proficient in System Verilog real number modeling
- Familiarity with writing regression tests for analog behavioral model verification
- Hands-on experience with UVM
- Familiarity with generating randomized vectors for analog behavioral model verification
- Familiar with developing checkers & writing assertions
- Experience with running mixed signal - DMS simulations and developing System Verilog and EEnet based analog models
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