At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
What you will do -
You'll be joining our Application Engineering Team, which is responsible for acheiving best in class Power Peformance Area (PPA) for our key customers using Cadence Implementation Tools
Be able to seasmlessly assimilate to different customer flows to drive Physical Implementation flows.
Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules
Conduct technical presentations and product demonstrations
Drive technical evaluations / benchmarks to success
Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements
Drive adoption and proliferation of Cadence tools and technologies
Amend and augment the flow as needed using Tcl and / or other programming skills to meet objectives and improve results / flows
Capture best practices and lessons learned from current evaluations / benchmarks and utilize to improve efficiency and success rate in next engagements
What we want to see -
You are a Physical Design Engineer with 7+ years of experience.
Have a keen eye for debugging issues around Physical Design and have a penchant for looking for best in class PPA with out of box thinking
Have experience with pushing PPA for CPU or GPU style designs
Experience running P&R tools like Innovus / ICC2
Experience running synthesis tools like Genus / DC
Experience in Block-level and Full-chip floor-planning and power grid planning, block and top level clock planning and power reduction techniques
Experience with TCL programming
We’re doing work that matters. Help us solve what others can’t.
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