FPGA / RTL Design Engineer III (W2 Only)
Contract
Location : Hillsboro, OR
Duration : 4 + Months
Job Description :
Have you got the right qualifications and skills for this job Find out below, and hit apply to be considered.
This is a senior RTL design engineer position. Primary responsibilities include :
- Working with IP designers and DFx engineers to define and scope design requirements and develop specifications for testing a given IP on a test chip.
- Implementing the above mentioned spec / design in RTL.
- Working with pre-silicon verification team to develop test-plans and verification collaterals.
- Working with the physical design team for floor-plan and timing convergence.
- Working with post-silicon validation teams to resolve silicon-level sightings.
- Working with IP designers and 3rd party IP vendors to define and develop specifications for evaluating / testing inter-operability of soft IPs (e.
g., DDR memory controllers) with Intel Hard IP.
You should possess a Bachelor or a Master degree in Electrical Engineering with at least 8+ years of relevant industry experience.
Additional qualifications include :
- Previous design experience with ARM based SoC, including AXI / ACE and APB bus protocols.
- Experience in HDL design with Verilog / SystemVerilog.
- Experience with ASIC and / or SoC design flows and methodology, including CPF / UPF flows.
- Experience with industry standard RTL design, simulation, and formal verification tools.
- Experience in synthesis and development of timing constraints.
- Scripting abilities (perl / tcl).
- Strong written / verbal communication skills are a must, as you will be working, influencing and collaborating with teams.
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FPGA/RTL Design Engineer – III (W2 Only)
FPGA/RTL Design Engineer – III (W2 Only). This is a senior RTL design engineer position. Working with IP designers and DFx engineers to define and scope design requirements and develop specifications for testing a given IP on a test chip. Implementing the above mentioned spec/design in RTL. ...
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