Responsibilities :
Run Logic / Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power.
Debug the timing / area / congestion issues and work with RTL & Physical designers to resolve them.
- Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures.
- Perform RTL Lint and work with the Designers to create waivers.
- Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC.
- Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks.
- Develop Power Intent Specification in UPF for the multi-Vdd designs.
- Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power).
Minimum Qualifications :
- 8+ years of experience
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- Experience with RTL Synthesis and design optimization for Power, Performance, Area.
- Knowledge of front-end and back-end ASIC tools.
- Experience with RTL design using System Verilog or other HDL.
- Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues.
- Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows for complex environments.
- Experience with communicating across functional internal teams and vendors.
Preferred Qualifications :
- Knowledge of Clock Domain Crossing, Reset Domain Crossing, LEC.
- 5+ years of experience in Design Integration and Front-End Implementation.
- Synthesis Background, Timing Constraints Development, Floor planning and STA.
- Experience Knowledge of RTL coding using Verilog / System Verilog.
- Knowledge of Timing / physical libraries, SRAM Memories.
- Experience with Power, Performance, Area Analysis and techniques for reducing power.
- Experience with Design Compiler, Spyglass, Primetime, Formality or equivalent tools.
- Scripting and programming experience using Perl / Python, TCL, and Make.
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